2381 	struct radeon_bo_list *src_reloc, *dst_reloc;  in r600_dma_cs_parse()  local
2402 			r = r600_dma_cs_next_reloc(p, &dst_reloc);  in r600_dma_cs_parse()
2411 				ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2417 				ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2418 				ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2421 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2423 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2433 			r = r600_dma_cs_next_reloc(p, &dst_reloc);  in r600_dma_cs_parse()
2449 					ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2450 					ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2460 					ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);  in r600_dma_cs_parse()
2470 					ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2472 					ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;  in r600_dma_cs_parse()
2481 					ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2484 					ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16;  in r600_dma_cs_parse()
2493 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2495 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2504 			r = r600_dma_cs_next_reloc(p, &dst_reloc);  in r600_dma_cs_parse()
2511 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2513 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2516 			ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);  in r600_dma_cs_parse()
2517 			ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;  in r600_dma_cs_parse()