2385 	u64 src_offset, dst_offset;  in r600_dma_cs_parse()  local
2408 				dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2409 				dst_offset <<= 8;  in r600_dma_cs_parse()
2414 				dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2415 				dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;  in r600_dma_cs_parse()
2421 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2423 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2447 					dst_offset = radeon_get_ib_value(p, idx+5);  in r600_dma_cs_parse()
2448 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;  in r600_dma_cs_parse()
2458 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2459 					dst_offset <<= 8;  in r600_dma_cs_parse()
2467 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2468 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;  in r600_dma_cs_parse()
2478 					dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2479 					dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;  in r600_dma_cs_parse()
2493 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2495 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()
2509 			dst_offset = radeon_get_ib_value(p, idx+1);  in r600_dma_cs_parse()
2510 			dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;  in r600_dma_cs_parse()
2511 			if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {  in r600_dma_cs_parse()
2513 					 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));  in r600_dma_cs_parse()