Lines Matching refs:db_depth_info
71 u32 db_depth_info; member
330 track->db_depth_info = 7 | (1 << 25); in r600_cs_track_init()
534 switch (G_028010_FORMAT(track->db_depth_info)) { in r600_cs_track_validate_db()
549 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info)); in r600_cs_track_validate_db()
576 array_mode = G_028010_ARRAY_MODE(track->db_depth_info); in r600_cs_track_validate_db()
586 G_028010_ARRAY_MODE(track->db_depth_info), in r600_cs_track_validate_db()
587 track->db_depth_info); in r600_cs_track_validate_db()
599 G_028010_ARRAY_MODE(track->db_depth_info), in r600_cs_track_validate_db()
600 track->db_depth_info); in r600_cs_track_validate_db()
633 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) { in r600_cs_track_validate_db()
639 __func__, __LINE__, track->db_depth_info); in r600_cs_track_validate_db()
774 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID && in r600_cs_track_check()
1041 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()
1043 track->db_depth_info &= C_028010_ARRAY_MODE; in r600_cs_check_reg()
1046 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1); in r600_cs_check_reg()
1049 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); in r600_cs_check_reg()
1052 track->db_depth_info = radeon_get_ib_value(p, idx); in r600_cs_check_reg()