629 	struct radeon_bo_list *reloc;  in r300_packet0_check()  local
663 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
670 		track->cb[i].robj = reloc->robj;  in r300_packet0_check()
673 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
676 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
683 		track->zb.robj = reloc->robj;  in r300_packet0_check()
686 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
705 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
715 				  ((idx_value & ~31) + (u32)reloc->gpu_offset);  in r300_packet0_check()
717 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
719 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
721 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
724 			tmp = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
728 		track->textures[i].robj = reloc->robj;  in r300_packet0_check()
778 			r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
786 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
788 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
790 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
863 			r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
871 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r300_packet0_check()
873 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r300_packet0_check()
875 			else if (reloc->tiling_flags & RADEON_TILING_MICRO_SQUARE)  in r300_packet0_check()
1078 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
1085 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1120 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet0_check()
1127 		track->aa.robj = reloc->robj;  in r300_packet0_check()
1130 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1173 	struct radeon_bo_list *reloc;  in r300_packet3_check()  local
1189 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r300_packet3_check()
1195 		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);  in r300_packet3_check()
1196 		r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);  in r300_packet3_check()