635 	u32 idx_value;  in r300_packet0_check()  local
639 	idx_value = radeon_get_ib_value(p, idx);  in r300_packet0_check()
671 		track->cb[i].offset = idx_value;  in r300_packet0_check()
673 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
684 		track->zb.offset = idx_value;  in r300_packet0_check()
686 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
714 			ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */  in r300_packet0_check()
715 				  ((idx_value & ~31) + (u32)reloc->gpu_offset);  in r300_packet0_check()
724 			tmp = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
734 		track->vap_vf_cntl = idx_value;  in r300_packet0_check()
738 		track->vtx_size = idx_value & 0x7F;  in r300_packet0_check()
742 		track->max_indx = idx_value & 0x00FFFFFFUL;  in r300_packet0_check()
748 		track->vap_alt_nverts = idx_value & 0xFFFFFF;  in r300_packet0_check()
752 		track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;  in r300_packet0_check()
761 		if ((idx_value & (1 << 10)) && /* CMASK_ENABLE */  in r300_packet0_check()
766 		track->num_cb = ((idx_value >> 5) & 0x3) + 1;  in r300_packet0_check()
793 			tmp = idx_value & ~(0x7 << 16);  in r300_packet0_check()
798 		track->cb[i].pitch = idx_value & 0x3FFE;  in r300_packet0_check()
799 		switch (((idx_value >> 21) & 0xF)) {  in r300_packet0_check()
814 					  ((idx_value >> 21) & 0xF));  in r300_packet0_check()
829 				  ((idx_value >> 21) & 0xF));  in r300_packet0_check()
836 		if (idx_value & 2) {  in r300_packet0_check()
845 		switch ((idx_value & 0xF)) {  in r300_packet0_check()
855 				  (idx_value & 0xF));  in r300_packet0_check()
878 			tmp = idx_value & ~(0x7 << 16);  in r300_packet0_check()
882 		track->zb.pitch = idx_value & 0x3FFC;  in r300_packet0_check()
890 			enabled = !!(idx_value & (1 << i));  in r300_packet0_check()
913 		tmp = (idx_value >> 25) & 0x3;  in r300_packet0_check()
915 		switch ((idx_value & 0x1F)) {  in r300_packet0_check()
964 					  (idx_value & 0x1F));  in r300_packet0_check()
976 				  (idx_value & 0x1F));  in r300_packet0_check()
999 		tmp = idx_value & 0x7;  in r300_packet0_check()
1003 		tmp = (idx_value >> 3) & 0x7;  in r300_packet0_check()
1027 		tmp = idx_value & 0x3FFF;  in r300_packet0_check()
1030 			tmp = ((idx_value >> 15) & 1) << 11;  in r300_packet0_check()
1032 			tmp = ((idx_value >> 16) & 1) << 11;  in r300_packet0_check()
1036 			if (idx_value & (1 << 14)) {  in r300_packet0_check()
1041 		} else if (idx_value & (1 << 14)) {  in r300_packet0_check()
1065 		tmp = idx_value & 0x7FF;  in r300_packet0_check()
1067 		tmp = (idx_value >> 11) & 0x7FF;  in r300_packet0_check()
1069 		tmp = (idx_value >> 26) & 0xF;  in r300_packet0_check()
1071 		tmp = idx_value & (1 << 31);  in r300_packet0_check()
1073 		tmp = (idx_value >> 22) & 0xF;  in r300_packet0_check()
1085 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1089 		track->color_channel_mask = idx_value;  in r300_packet0_check()
1097 			if (idx_value & 0x1)  in r300_packet0_check()
1098 				ib[idx] = idx_value & ~1;  in r300_packet0_check()
1103 		track->zb_cb_clear = !!(idx_value & (1 << 5));  in r300_packet0_check()
1107 			if (idx_value & (R300_HIZ_ENABLE |  in r300_packet0_check()
1116 		track->blend_read_enable = !!(idx_value & (1 << 2));  in r300_packet0_check()
1128 		track->aa.offset = idx_value;  in r300_packet0_check()
1130 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r300_packet0_check()
1133 		track->aa.pitch = idx_value & 0x3FFE;  in r300_packet0_check()
1137 		track->aaresolve = idx_value & 0x1;  in r300_packet0_check()
1144 		if (idx_value && (p->rdev->hyperz_filp != p->filp))  in r300_packet0_check()
1148 		if (idx_value && (p->rdev->hyperz_filp != p->filp))  in r300_packet0_check()
1166 	       reg, idx, idx_value);  in r300_packet0_check()