1261 	struct radeon_bo_list *reloc;  in r100_reloc_pitch_offset()  local
1264 	r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_reloc_pitch_offset()
1274 	tmp += (((u32)reloc->gpu_offset) >> 10);  in r100_reloc_pitch_offset()
1277 		if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r100_reloc_pitch_offset()
1279 		if (reloc->tiling_flags & RADEON_TILING_MICRO) {  in r100_reloc_pitch_offset()
1300 	struct radeon_bo_list *reloc;  in r100_packet3_load_vbpntr()  local
1317 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet3_load_vbpntr()
1325 		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);  in r100_packet3_load_vbpntr()
1328 		track->arrays[i + 0].robj = reloc->robj;  in r100_packet3_load_vbpntr()
1330 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet3_load_vbpntr()
1337 		ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);  in r100_packet3_load_vbpntr()
1338 		track->arrays[i + 1].robj = reloc->robj;  in r100_packet3_load_vbpntr()
1343 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet3_load_vbpntr()
1351 		ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);  in r100_packet3_load_vbpntr()
1352 		track->arrays[i + 0].robj = reloc->robj;  in r100_packet3_load_vbpntr()
1549 	struct radeon_bo_list *reloc;  in r100_packet0_check()  local
1582 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1589 		track->zb.robj = reloc->robj;  in r100_packet0_check()
1592 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1595 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1602 		track->cb[0].robj = reloc->robj;  in r100_packet0_check()
1605 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1611 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1619 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r100_packet0_check()
1621 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r100_packet0_check()
1626 			ib[idx] = tmp + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1628 			ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1629 		track->textures[i].robj = reloc->robj;  in r100_packet0_check()
1638 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1646 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1647 		track->textures[0].cube_info[i].robj = reloc->robj;  in r100_packet0_check()
1656 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1664 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1665 		track->textures[1].cube_info[i].robj = reloc->robj;  in r100_packet0_check()
1674 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1682 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1683 		track->textures[2].cube_info[i].robj = reloc->robj;  in r100_packet0_check()
1692 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1700 			if (reloc->tiling_flags & RADEON_TILING_MACRO)  in r100_packet0_check()
1702 			if (reloc->tiling_flags & RADEON_TILING_MICRO)  in r100_packet0_check()
1763 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet0_check()
1770 		ib[idx] = idx_value + ((u32)reloc->gpu_offset);  in r100_packet0_check()
1907 	struct radeon_bo_list *reloc;  in r100_packet3_check()  local
1923 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet3_check()
1929 		ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);  in r100_packet3_check()
1930 		r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);  in r100_packet3_check()
1937 		r = radeon_cs_packet_next_reloc(p, &reloc, 0);  in r100_packet3_check()
1943 		ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);  in r100_packet3_check()
1947 		track->arrays[0].robj = reloc->robj;  in r100_packet3_check()