Lines Matching refs:idx_value
1304 u32 idx_value; in r100_packet3_load_vbpntr() local
1324 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1327 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1339 track->arrays[i + 1].esize = idx_value >> 24; in r100_packet3_load_vbpntr()
1350 idx_value = radeon_get_ib_value(p, idx); in r100_packet3_load_vbpntr()
1353 track->arrays[i + 0].esize = idx_value >> 8; in r100_packet3_load_vbpntr()
1556 u32 idx_value; in r100_packet0_check() local
1561 idx_value = radeon_get_ib_value(p, idx); in r100_packet0_check()
1590 track->zb.offset = idx_value; in r100_packet0_check()
1592 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1603 track->cb[0].offset = idx_value; in r100_packet0_check()
1605 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1624 tmp = idx_value & ~(0x7 << 2); in r100_packet0_check()
1628 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1645 track->textures[0].cube_info[i].offset = idx_value; in r100_packet0_check()
1646 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1663 track->textures[1].cube_info[i].offset = idx_value; in r100_packet0_check()
1664 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1681 track->textures[2].cube_info[i].offset = idx_value; in r100_packet0_check()
1682 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1687 track->maxy = ((idx_value >> 16) & 0x7FF); in r100_packet0_check()
1705 tmp = idx_value & ~(0x7 << 16); in r100_packet0_check()
1709 ib[idx] = idx_value; in r100_packet0_check()
1711 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; in r100_packet0_check()
1715 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK; in r100_packet0_check()
1719 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) { in r100_packet0_check()
1737 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f)); in r100_packet0_check()
1740 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE); in r100_packet0_check()
1745 switch (idx_value & 0xf) { in r100_packet0_check()
1770 ib[idx] = idx_value + ((u32)reloc->gpu_offset); in r100_packet0_check()
1774 uint32_t temp = idx_value >> 4; in r100_packet0_check()
1781 track->vap_vf_cntl = idx_value; in r100_packet0_check()
1784 track->vtx_size = r100_get_vtx_size(idx_value); in r100_packet0_check()
1790 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1; in r100_packet0_check()
1791 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1; in r100_packet0_check()
1798 track->textures[i].pitch = idx_value + 32; in r100_packet0_check()
1805 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK) in r100_packet0_check()
1807 tmp = (idx_value >> 23) & 0x7; in r100_packet0_check()
1810 tmp = (idx_value >> 27) & 0x7; in r100_packet0_check()
1819 if (idx_value & RADEON_TXFORMAT_NON_POWER2) { in r100_packet0_check()
1823 …track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDT… in r100_packet0_check()
1824 …track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HE… in r100_packet0_check()
1826 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE) in r100_packet0_check()
1828 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) { in r100_packet0_check()
1864 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf); in r100_packet0_check()
1865 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf); in r100_packet0_check()
1871 tmp = idx_value; in r100_packet0_check()