2294 			       NISLANDS_SMC_SWSTATE *smc_state)  in ni_populate_smc_sp()  argument
2301 		smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);  in ni_populate_smc_sp()
2303 	smc_state->levels[ps->performance_level_count - 1].bSP =  in ni_populate_smc_sp()
2390 			     NISLANDS_SMC_SWSTATE *smc_state)  in ni_populate_smc_t()  argument
2405 		smc_state->levels[0].aT = cpu_to_be32(a_t);  in ni_populate_smc_t()
2409 	smc_state->levels[0].aT = cpu_to_be32(0);  in ni_populate_smc_t()
2434 		a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;  in ni_populate_smc_t()
2436 		smc_state->levels[i].aT = cpu_to_be32(a_t);  in ni_populate_smc_t()
2442 		smc_state->levels[i + 1].aT = cpu_to_be32(a_t);  in ni_populate_smc_t()
2450 						NISLANDS_SMC_SWSTATE *smc_state)  in ni_populate_power_containment_values()  argument
2471 	if (smc_state->levelCount != state->performance_level_count)  in ni_populate_power_containment_values()
2493 	smc_state->levels[0].dpm2.MaxPS = 0;  in ni_populate_power_containment_values()
2494 	smc_state->levels[0].dpm2.NearTDPDec = 0;  in ni_populate_power_containment_values()
2495 	smc_state->levels[0].dpm2.AboveSafeInc = 0;  in ni_populate_power_containment_values()
2496 	smc_state->levels[0].dpm2.BelowSafeInc = 0;  in ni_populate_power_containment_values()
2497 	smc_state->levels[0].stateFlags |= power_boost_limit ? PPSMC_STATEFLAG_POWERBOOST : 0;  in ni_populate_power_containment_values()
2521 		smc_state->levels[i].dpm2.MaxPS =  in ni_populate_power_containment_values()
2523 		smc_state->levels[i].dpm2.NearTDPDec = NISLANDS_DPM2_NEAR_TDP_DEC;  in ni_populate_power_containment_values()
2524 		smc_state->levels[i].dpm2.AboveSafeInc = NISLANDS_DPM2_ABOVE_SAFE_INC;  in ni_populate_power_containment_values()
2525 		smc_state->levels[i].dpm2.BelowSafeInc = NISLANDS_DPM2_BELOW_SAFE_INC;  in ni_populate_power_containment_values()
2526 		smc_state->levels[i].stateFlags |=  in ni_populate_power_containment_values()
2536 					 NISLANDS_SMC_SWSTATE *smc_state)  in ni_populate_sq_ramping_values()  argument
2548 	if (smc_state->levelCount != state->performance_level_count)  in ni_populate_sq_ramping_values()
2585 		smc_state->levels[i].SQPowerThrottle   = cpu_to_be32(sq_power_throttle);  in ni_populate_sq_ramping_values()
2586 		smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);  in ni_populate_sq_ramping_values()
2624 					 NISLANDS_SMC_SWSTATE *smc_state)  in ni_convert_power_state_to_smc()  argument
2633 		smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;  in ni_convert_power_state_to_smc()
2635 	smc_state->levelCount = 0;  in ni_convert_power_state_to_smc()
2642 						    &smc_state->levels[i]);  in ni_convert_power_state_to_smc()
2643 		smc_state->levels[i].arbRefreshState =  in ni_convert_power_state_to_smc()
2650 			smc_state->levels[i].displayWatermark =  in ni_convert_power_state_to_smc()
2654 			smc_state->levels[i].displayWatermark = (i < 2) ?  in ni_convert_power_state_to_smc()
2658 			smc_state->levels[i].ACIndex = NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;  in ni_convert_power_state_to_smc()
2660 			smc_state->levels[i].ACIndex = 0;  in ni_convert_power_state_to_smc()
2662 		smc_state->levelCount++;  in ni_convert_power_state_to_smc()
2668 	ni_populate_smc_sp(rdev, radeon_state, smc_state);  in ni_convert_power_state_to_smc()
2670 	ret = ni_populate_power_containment_values(rdev, radeon_state, smc_state);  in ni_convert_power_state_to_smc()
2674 	ret = ni_populate_sq_ramping_values(rdev, radeon_state, smc_state);  in ni_convert_power_state_to_smc()
2678 	return ni_populate_smc_t(rdev, radeon_state, smc_state);  in ni_convert_power_state_to_smc()
2690 	NISLANDS_SMC_SWSTATE *smc_state = kzalloc(state_size, GFP_KERNEL);  in ni_upload_sw_state()  local
2692 	if (smc_state == NULL)  in ni_upload_sw_state()
2695 	ret = ni_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);  in ni_upload_sw_state()
2699 	ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end);  in ni_upload_sw_state()
2702 	kfree(smc_state);  in ni_upload_sw_state()