1745 	u32 reset_mask = 0;  in cayman_gpu_check_soft_reset()  local
1756 		reset_mask |= RADEON_RESET_GFX;  in cayman_gpu_check_soft_reset()
1760 		reset_mask |= RADEON_RESET_CP;  in cayman_gpu_check_soft_reset()
1763 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in cayman_gpu_check_soft_reset()
1768 		reset_mask |= RADEON_RESET_DMA;  in cayman_gpu_check_soft_reset()
1773 		reset_mask |= RADEON_RESET_DMA1;  in cayman_gpu_check_soft_reset()
1778 		reset_mask |= RADEON_RESET_DMA;  in cayman_gpu_check_soft_reset()
1781 		reset_mask |= RADEON_RESET_DMA1;  in cayman_gpu_check_soft_reset()
1786 		reset_mask |= RADEON_RESET_RLC;  in cayman_gpu_check_soft_reset()
1789 		reset_mask |= RADEON_RESET_IH;  in cayman_gpu_check_soft_reset()
1792 		reset_mask |= RADEON_RESET_SEM;  in cayman_gpu_check_soft_reset()
1795 		reset_mask |= RADEON_RESET_GRBM;  in cayman_gpu_check_soft_reset()
1798 		reset_mask |= RADEON_RESET_VMC;  in cayman_gpu_check_soft_reset()
1802 		reset_mask |= RADEON_RESET_MC;  in cayman_gpu_check_soft_reset()
1805 		reset_mask |= RADEON_RESET_DISPLAY;  in cayman_gpu_check_soft_reset()
1810 		reset_mask |= RADEON_RESET_VMC;  in cayman_gpu_check_soft_reset()
1813 	if (reset_mask & RADEON_RESET_MC) {  in cayman_gpu_check_soft_reset()
1814 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in cayman_gpu_check_soft_reset()
1815 		reset_mask &= ~RADEON_RESET_MC;  in cayman_gpu_check_soft_reset()
1818 	return reset_mask;  in cayman_gpu_check_soft_reset()
1821 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in cayman_gpu_soft_reset()  argument
1827 	if (reset_mask == 0)  in cayman_gpu_soft_reset()
1830 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in cayman_gpu_soft_reset()
1845 	if (reset_mask & RADEON_RESET_DMA) {  in cayman_gpu_soft_reset()
1852 	if (reset_mask & RADEON_RESET_DMA1) {  in cayman_gpu_soft_reset()
1866 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {  in cayman_gpu_soft_reset()
1881 	if (reset_mask & RADEON_RESET_CP) {  in cayman_gpu_soft_reset()
1887 	if (reset_mask & RADEON_RESET_DMA)  in cayman_gpu_soft_reset()
1890 	if (reset_mask & RADEON_RESET_DMA1)  in cayman_gpu_soft_reset()
1893 	if (reset_mask & RADEON_RESET_DISPLAY)  in cayman_gpu_soft_reset()
1896 	if (reset_mask & RADEON_RESET_RLC)  in cayman_gpu_soft_reset()
1899 	if (reset_mask & RADEON_RESET_SEM)  in cayman_gpu_soft_reset()
1902 	if (reset_mask & RADEON_RESET_IH)  in cayman_gpu_soft_reset()
1905 	if (reset_mask & RADEON_RESET_GRBM)  in cayman_gpu_soft_reset()
1908 	if (reset_mask & RADEON_RESET_VMC)  in cayman_gpu_soft_reset()
1912 		if (reset_mask & RADEON_RESET_MC)  in cayman_gpu_soft_reset()
1955 	u32 reset_mask;  in cayman_asic_reset()  local
1962 	reset_mask = cayman_gpu_check_soft_reset(rdev);  in cayman_asic_reset()
1964 	if (reset_mask)  in cayman_asic_reset()
1967 	cayman_gpu_soft_reset(rdev, reset_mask);  in cayman_asic_reset()
1969 	reset_mask = cayman_gpu_check_soft_reset(rdev);  in cayman_asic_reset()
1971 	if (reset_mask)  in cayman_asic_reset()
1990 	u32 reset_mask = cayman_gpu_check_soft_reset(rdev);  in cayman_gfx_is_lockup()  local
1992 	if (!(reset_mask & (RADEON_RESET_GFX |  in cayman_gfx_is_lockup()