Lines Matching refs:rdev
42 u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg) in tn_smc_rreg() argument
47 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
50 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_rreg()
54 void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v) in tn_smc_wreg() argument
58 spin_lock_irqsave(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
61 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags); in tn_smc_wreg()
190 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
191 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
192 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
193 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
194 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
195 extern void evergreen_mc_program(struct radeon_device *rdev);
196 extern void evergreen_irq_suspend(struct radeon_device *rdev);
197 extern int evergreen_mc_init(struct radeon_device *rdev);
198 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
199 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
200 extern void evergreen_program_aspm(struct radeon_device *rdev);
201 extern void sumo_rlc_fini(struct radeon_device *rdev);
202 extern int sumo_rlc_init(struct radeon_device *rdev);
203 extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev);
453 static void ni_init_golden_registers(struct radeon_device *rdev) in ni_init_golden_registers() argument
455 switch (rdev->family) { in ni_init_golden_registers()
457 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
460 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
465 if ((rdev->pdev->device == 0x9900) || in ni_init_golden_registers()
466 (rdev->pdev->device == 0x9901) || in ni_init_golden_registers()
467 (rdev->pdev->device == 0x9903) || in ni_init_golden_registers()
468 (rdev->pdev->device == 0x9904) || in ni_init_golden_registers()
469 (rdev->pdev->device == 0x9905) || in ni_init_golden_registers()
470 (rdev->pdev->device == 0x9906) || in ni_init_golden_registers()
471 (rdev->pdev->device == 0x9907) || in ni_init_golden_registers()
472 (rdev->pdev->device == 0x9908) || in ni_init_golden_registers()
473 (rdev->pdev->device == 0x9909) || in ni_init_golden_registers()
474 (rdev->pdev->device == 0x990A) || in ni_init_golden_registers()
475 (rdev->pdev->device == 0x990B) || in ni_init_golden_registers()
476 (rdev->pdev->device == 0x990C) || in ni_init_golden_registers()
477 (rdev->pdev->device == 0x990D) || in ni_init_golden_registers()
478 (rdev->pdev->device == 0x990E) || in ni_init_golden_registers()
479 (rdev->pdev->device == 0x990F) || in ni_init_golden_registers()
480 (rdev->pdev->device == 0x9910) || in ni_init_golden_registers()
481 (rdev->pdev->device == 0x9913) || in ni_init_golden_registers()
482 (rdev->pdev->device == 0x9917) || in ni_init_golden_registers()
483 (rdev->pdev->device == 0x9918)) { in ni_init_golden_registers()
484 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
487 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
491 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
494 radeon_program_register_sequence(rdev, in ni_init_golden_registers()
634 int ni_mc_load_microcode(struct radeon_device *rdev) in ni_mc_load_microcode() argument
641 if (!rdev->mc_fw) in ni_mc_load_microcode()
644 switch (rdev->family) { in ni_mc_load_microcode()
687 fw_data = (const __be32 *)rdev->mc_fw->data; in ni_mc_load_microcode()
697 for (i = 0; i < rdev->usec_timeout; i++) { in ni_mc_load_microcode()
710 int ni_init_microcode(struct radeon_device *rdev) in ni_init_microcode() argument
721 switch (rdev->family) { in ni_init_microcode()
773 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev); in ni_init_microcode()
776 if (rdev->pfp_fw->size != pfp_req_size) { in ni_init_microcode()
778 rdev->pfp_fw->size, fw_name); in ni_init_microcode()
784 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev); in ni_init_microcode()
787 if (rdev->me_fw->size != me_req_size) { in ni_init_microcode()
789 rdev->me_fw->size, fw_name); in ni_init_microcode()
794 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev); in ni_init_microcode()
797 if (rdev->rlc_fw->size != rlc_req_size) { in ni_init_microcode()
799 rdev->rlc_fw->size, fw_name); in ni_init_microcode()
804 if (!(rdev->flags & RADEON_IS_IGP)) { in ni_init_microcode()
806 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev); in ni_init_microcode()
809 if (rdev->mc_fw->size != mc_req_size) { in ni_init_microcode()
811 rdev->mc_fw->size, fw_name); in ni_init_microcode()
816 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) { in ni_init_microcode()
818 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev); in ni_init_microcode()
821 release_firmware(rdev->smc_fw); in ni_init_microcode()
822 rdev->smc_fw = NULL; in ni_init_microcode()
824 } else if (rdev->smc_fw->size != smc_req_size) { in ni_init_microcode()
826 rdev->mc_fw->size, fw_name); in ni_init_microcode()
836 release_firmware(rdev->pfp_fw); in ni_init_microcode()
837 rdev->pfp_fw = NULL; in ni_init_microcode()
838 release_firmware(rdev->me_fw); in ni_init_microcode()
839 rdev->me_fw = NULL; in ni_init_microcode()
840 release_firmware(rdev->rlc_fw); in ni_init_microcode()
841 rdev->rlc_fw = NULL; in ni_init_microcode()
842 release_firmware(rdev->mc_fw); in ni_init_microcode()
843 rdev->mc_fw = NULL; in ni_init_microcode()
858 int cayman_get_allowed_info_register(struct radeon_device *rdev, in cayman_get_allowed_info_register() argument
877 int tn_get_temp(struct radeon_device *rdev) in tn_get_temp() argument
888 static void cayman_gpu_init(struct radeon_device *rdev) in cayman_gpu_init() argument
901 switch (rdev->family) { in cayman_gpu_init()
903 rdev->config.cayman.max_shader_engines = 2; in cayman_gpu_init()
904 rdev->config.cayman.max_pipes_per_simd = 4; in cayman_gpu_init()
905 rdev->config.cayman.max_tile_pipes = 8; in cayman_gpu_init()
906 rdev->config.cayman.max_simds_per_se = 12; in cayman_gpu_init()
907 rdev->config.cayman.max_backends_per_se = 4; in cayman_gpu_init()
908 rdev->config.cayman.max_texture_channel_caches = 8; in cayman_gpu_init()
909 rdev->config.cayman.max_gprs = 256; in cayman_gpu_init()
910 rdev->config.cayman.max_threads = 256; in cayman_gpu_init()
911 rdev->config.cayman.max_gs_threads = 32; in cayman_gpu_init()
912 rdev->config.cayman.max_stack_entries = 512; in cayman_gpu_init()
913 rdev->config.cayman.sx_num_of_sets = 8; in cayman_gpu_init()
914 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
915 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
916 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
917 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
918 rdev->config.cayman.sq_num_cf_insts = 2; in cayman_gpu_init()
920 rdev->config.cayman.sc_prim_fifo_size = 0x100; in cayman_gpu_init()
921 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; in cayman_gpu_init()
922 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; in cayman_gpu_init()
927 rdev->config.cayman.max_shader_engines = 1; in cayman_gpu_init()
928 rdev->config.cayman.max_pipes_per_simd = 4; in cayman_gpu_init()
929 rdev->config.cayman.max_tile_pipes = 2; in cayman_gpu_init()
930 if ((rdev->pdev->device == 0x9900) || in cayman_gpu_init()
931 (rdev->pdev->device == 0x9901) || in cayman_gpu_init()
932 (rdev->pdev->device == 0x9905) || in cayman_gpu_init()
933 (rdev->pdev->device == 0x9906) || in cayman_gpu_init()
934 (rdev->pdev->device == 0x9907) || in cayman_gpu_init()
935 (rdev->pdev->device == 0x9908) || in cayman_gpu_init()
936 (rdev->pdev->device == 0x9909) || in cayman_gpu_init()
937 (rdev->pdev->device == 0x990B) || in cayman_gpu_init()
938 (rdev->pdev->device == 0x990C) || in cayman_gpu_init()
939 (rdev->pdev->device == 0x990F) || in cayman_gpu_init()
940 (rdev->pdev->device == 0x9910) || in cayman_gpu_init()
941 (rdev->pdev->device == 0x9917) || in cayman_gpu_init()
942 (rdev->pdev->device == 0x9999) || in cayman_gpu_init()
943 (rdev->pdev->device == 0x999C)) { in cayman_gpu_init()
944 rdev->config.cayman.max_simds_per_se = 6; in cayman_gpu_init()
945 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()
946 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
947 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
948 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
949 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
950 } else if ((rdev->pdev->device == 0x9903) || in cayman_gpu_init()
951 (rdev->pdev->device == 0x9904) || in cayman_gpu_init()
952 (rdev->pdev->device == 0x990A) || in cayman_gpu_init()
953 (rdev->pdev->device == 0x990D) || in cayman_gpu_init()
954 (rdev->pdev->device == 0x990E) || in cayman_gpu_init()
955 (rdev->pdev->device == 0x9913) || in cayman_gpu_init()
956 (rdev->pdev->device == 0x9918) || in cayman_gpu_init()
957 (rdev->pdev->device == 0x999D)) { in cayman_gpu_init()
958 rdev->config.cayman.max_simds_per_se = 4; in cayman_gpu_init()
959 rdev->config.cayman.max_backends_per_se = 2; in cayman_gpu_init()
960 rdev->config.cayman.max_hw_contexts = 8; in cayman_gpu_init()
961 rdev->config.cayman.sx_max_export_size = 256; in cayman_gpu_init()
962 rdev->config.cayman.sx_max_export_pos_size = 64; in cayman_gpu_init()
963 rdev->config.cayman.sx_max_export_smx_size = 192; in cayman_gpu_init()
964 } else if ((rdev->pdev->device == 0x9919) || in cayman_gpu_init()
965 (rdev->pdev->device == 0x9990) || in cayman_gpu_init()
966 (rdev->pdev->device == 0x9991) || in cayman_gpu_init()
967 (rdev->pdev->device == 0x9994) || in cayman_gpu_init()
968 (rdev->pdev->device == 0x9995) || in cayman_gpu_init()
969 (rdev->pdev->device == 0x9996) || in cayman_gpu_init()
970 (rdev->pdev->device == 0x999A) || in cayman_gpu_init()
971 (rdev->pdev->device == 0x99A0)) { in cayman_gpu_init()
972 rdev->config.cayman.max_simds_per_se = 3; in cayman_gpu_init()
973 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()
974 rdev->config.cayman.max_hw_contexts = 4; in cayman_gpu_init()
975 rdev->config.cayman.sx_max_export_size = 128; in cayman_gpu_init()
976 rdev->config.cayman.sx_max_export_pos_size = 32; in cayman_gpu_init()
977 rdev->config.cayman.sx_max_export_smx_size = 96; in cayman_gpu_init()
979 rdev->config.cayman.max_simds_per_se = 2; in cayman_gpu_init()
980 rdev->config.cayman.max_backends_per_se = 1; in cayman_gpu_init()
981 rdev->config.cayman.max_hw_contexts = 4; in cayman_gpu_init()
982 rdev->config.cayman.sx_max_export_size = 128; in cayman_gpu_init()
983 rdev->config.cayman.sx_max_export_pos_size = 32; in cayman_gpu_init()
984 rdev->config.cayman.sx_max_export_smx_size = 96; in cayman_gpu_init()
986 rdev->config.cayman.max_texture_channel_caches = 2; in cayman_gpu_init()
987 rdev->config.cayman.max_gprs = 256; in cayman_gpu_init()
988 rdev->config.cayman.max_threads = 256; in cayman_gpu_init()
989 rdev->config.cayman.max_gs_threads = 32; in cayman_gpu_init()
990 rdev->config.cayman.max_stack_entries = 512; in cayman_gpu_init()
991 rdev->config.cayman.sx_num_of_sets = 8; in cayman_gpu_init()
992 rdev->config.cayman.sq_num_cf_insts = 2; in cayman_gpu_init()
994 rdev->config.cayman.sc_prim_fifo_size = 0x40; in cayman_gpu_init()
995 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; in cayman_gpu_init()
996 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; in cayman_gpu_init()
1014 evergreen_fix_pci_max_read_req_size(rdev); in cayman_gpu_init()
1020 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024; in cayman_gpu_init()
1021 if (rdev->config.cayman.mem_row_size_in_kb > 4) in cayman_gpu_init()
1022 rdev->config.cayman.mem_row_size_in_kb = 4; in cayman_gpu_init()
1024 rdev->config.cayman.shader_engine_tile_size = 32; in cayman_gpu_init()
1025 rdev->config.cayman.num_gpus = 1; in cayman_gpu_init()
1026 rdev->config.cayman.multi_gpu_tile_size = 64; in cayman_gpu_init()
1029 rdev->config.cayman.num_tile_pipes = (1 << tmp); in cayman_gpu_init()
1031 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256; in cayman_gpu_init()
1033 rdev->config.cayman.num_shader_engines = tmp + 1; in cayman_gpu_init()
1035 rdev->config.cayman.num_gpus = tmp + 1; in cayman_gpu_init()
1037 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp; in cayman_gpu_init()
1039 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp; in cayman_gpu_init()
1049 rdev->config.cayman.tile_config = 0; in cayman_gpu_init()
1050 switch (rdev->config.cayman.num_tile_pipes) { in cayman_gpu_init()
1053 rdev->config.cayman.tile_config |= (0 << 0); in cayman_gpu_init()
1056 rdev->config.cayman.tile_config |= (1 << 0); in cayman_gpu_init()
1059 rdev->config.cayman.tile_config |= (2 << 0); in cayman_gpu_init()
1062 rdev->config.cayman.tile_config |= (3 << 0); in cayman_gpu_init()
1067 if (rdev->flags & RADEON_IS_IGP) in cayman_gpu_init()
1068 rdev->config.cayman.tile_config |= 1 << 4; in cayman_gpu_init()
1072 rdev->config.cayman.tile_config |= 0 << 4; in cayman_gpu_init()
1075 rdev->config.cayman.tile_config |= 1 << 4; in cayman_gpu_init()
1079 rdev->config.cayman.tile_config |= 2 << 4; in cayman_gpu_init()
1083 rdev->config.cayman.tile_config |= in cayman_gpu_init()
1085 rdev->config.cayman.tile_config |= in cayman_gpu_init()
1089 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) { in cayman_gpu_init()
1101 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()
1105 …for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines)… in cayman_gpu_init()
1109 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) { in cayman_gpu_init()
1115 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se; in cayman_gpu_init()
1119 rdev->config.cayman.active_simds = hweight32(~tmp); in cayman_gpu_init()
1126 if (ASIC_IS_DCE6(rdev)) in cayman_gpu_init()
1135 if ((rdev->config.cayman.max_backends_per_se == 1) && in cayman_gpu_init()
1136 (rdev->flags & RADEON_IS_IGP)) { in cayman_gpu_init()
1146 tmp = r6xx_remap_render_backend(rdev, tmp, in cayman_gpu_init()
1147 rdev->config.cayman.max_backends_per_se * in cayman_gpu_init()
1148 rdev->config.cayman.max_shader_engines, in cayman_gpu_init()
1151 rdev->config.cayman.backend_map = tmp; in cayman_gpu_init()
1155 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++) in cayman_gpu_init()
1177 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets); in cayman_gpu_init()
1193 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1… in cayman_gpu_init()
1194 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) | in cayman_gpu_init()
1195 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1))); in cayman_gpu_init()
1197 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) | in cayman_gpu_init()
1198 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) | in cayman_gpu_init()
1199 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size))); in cayman_gpu_init()
1206 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) | in cayman_gpu_init()
1249 if (rdev->family == CHIP_ARUBA) { in cayman_gpu_init()
1262 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev) in cayman_pcie_gart_tlb_flush() argument
1271 static int cayman_pcie_gart_enable(struct radeon_device *rdev) in cayman_pcie_gart_enable() argument
1275 if (rdev->gart.robj == NULL) { in cayman_pcie_gart_enable()
1276 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in cayman_pcie_gart_enable()
1279 r = radeon_gart_table_vram_pin(rdev); in cayman_pcie_gart_enable()
1302 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in cayman_pcie_gart_enable()
1303 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in cayman_pcie_gart_enable()
1304 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in cayman_pcie_gart_enable()
1306 (u32)(rdev->dummy_page.addr >> 12)); in cayman_pcie_gart_enable()
1323 rdev->vm_manager.max_pfn - 1); in cayman_pcie_gart_enable()
1325 rdev->vm_manager.saved_table_addr[i]); in cayman_pcie_gart_enable()
1330 (u32)(rdev->dummy_page.addr >> 12)); in cayman_pcie_gart_enable()
1347 cayman_pcie_gart_tlb_flush(rdev); in cayman_pcie_gart_enable()
1349 (unsigned)(rdev->mc.gtt_size >> 20), in cayman_pcie_gart_enable()
1350 (unsigned long long)rdev->gart.table_addr); in cayman_pcie_gart_enable()
1351 rdev->gart.ready = true; in cayman_pcie_gart_enable()
1355 static void cayman_pcie_gart_disable(struct radeon_device *rdev) in cayman_pcie_gart_disable() argument
1360 rdev->vm_manager.saved_table_addr[i] = RREG32( in cayman_pcie_gart_disable()
1379 radeon_gart_table_vram_unpin(rdev); in cayman_pcie_gart_disable()
1382 static void cayman_pcie_gart_fini(struct radeon_device *rdev) in cayman_pcie_gart_fini() argument
1384 cayman_pcie_gart_disable(rdev); in cayman_pcie_gart_fini()
1385 radeon_gart_table_vram_free(rdev); in cayman_pcie_gart_fini()
1386 radeon_gart_fini(rdev); in cayman_pcie_gart_fini()
1389 void cayman_cp_int_cntl_setup(struct radeon_device *rdev, in cayman_cp_int_cntl_setup() argument
1399 void cayman_fence_ring_emit(struct radeon_device *rdev, in cayman_fence_ring_emit() argument
1402 struct radeon_ring *ring = &rdev->ring[fence->ring]; in cayman_fence_ring_emit()
1403 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in cayman_fence_ring_emit()
1422 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) in cayman_ring_ib_execute() argument
1424 struct radeon_ring *ring = &rdev->ring[ib->ring]; in cayman_ring_ib_execute()
1458 static void cayman_cp_enable(struct radeon_device *rdev, bool enable) in cayman_cp_enable() argument
1463 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in cayman_cp_enable()
1464 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); in cayman_cp_enable()
1467 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_enable()
1471 u32 cayman_gfx_get_rptr(struct radeon_device *rdev, in cayman_gfx_get_rptr() argument
1476 if (rdev->wb.enabled) in cayman_gfx_get_rptr()
1477 rptr = rdev->wb.wb[ring->rptr_offs/4]; in cayman_gfx_get_rptr()
1490 u32 cayman_gfx_get_wptr(struct radeon_device *rdev, in cayman_gfx_get_wptr() argument
1505 void cayman_gfx_set_wptr(struct radeon_device *rdev, in cayman_gfx_set_wptr() argument
1520 static int cayman_cp_load_microcode(struct radeon_device *rdev) in cayman_cp_load_microcode() argument
1525 if (!rdev->me_fw || !rdev->pfp_fw) in cayman_cp_load_microcode()
1528 cayman_cp_enable(rdev, false); in cayman_cp_load_microcode()
1530 fw_data = (const __be32 *)rdev->pfp_fw->data; in cayman_cp_load_microcode()
1536 fw_data = (const __be32 *)rdev->me_fw->data; in cayman_cp_load_microcode()
1547 static int cayman_cp_start(struct radeon_device *rdev) in cayman_cp_start() argument
1549 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_start()
1552 r = radeon_ring_lock(rdev, ring, 7); in cayman_cp_start()
1560 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1); in cayman_cp_start()
1564 radeon_ring_unlock_commit(rdev, ring, false); in cayman_cp_start()
1566 cayman_cp_enable(rdev, true); in cayman_cp_start()
1568 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19); in cayman_cp_start()
1606 radeon_ring_unlock_commit(rdev, ring, false); in cayman_cp_start()
1613 static void cayman_cp_fini(struct radeon_device *rdev) in cayman_cp_fini() argument
1615 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_cp_fini()
1616 cayman_cp_enable(rdev, false); in cayman_cp_fini()
1617 radeon_ring_fini(rdev, ring); in cayman_cp_fini()
1618 radeon_scratch_free(rdev, ring->rptr_save_reg); in cayman_cp_fini()
1621 static int cayman_cp_resume(struct radeon_device *rdev) in cayman_cp_resume() argument
1682 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in cayman_cp_resume()
1690 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1699 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET; in cayman_cp_resume()
1706 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1712 ring = &rdev->ring[ridx[i]]; in cayman_cp_resume()
1724 cayman_cp_start(rdev); in cayman_cp_resume()
1725 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true; in cayman_cp_resume()
1726 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1727 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1729 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]); in cayman_cp_resume()
1731 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false; in cayman_cp_resume()
1732 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false; in cayman_cp_resume()
1733 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false; in cayman_cp_resume()
1737 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX) in cayman_cp_resume()
1738 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); in cayman_cp_resume()
1743 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev) in cayman_gpu_check_soft_reset() argument
1804 if (evergreen_is_display_hung(rdev)) in cayman_gpu_check_soft_reset()
1821 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) in cayman_gpu_soft_reset() argument
1830 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in cayman_gpu_soft_reset()
1832 evergreen_print_gpu_status_regs(rdev); in cayman_gpu_soft_reset()
1833 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n", in cayman_gpu_soft_reset()
1835 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n", in cayman_gpu_soft_reset()
1837 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in cayman_gpu_soft_reset()
1839 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in cayman_gpu_soft_reset()
1861 evergreen_mc_stop(rdev, &save); in cayman_gpu_soft_reset()
1862 if (evergreen_mc_wait_for_idle(rdev)) { in cayman_gpu_soft_reset()
1863 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in cayman_gpu_soft_reset()
1911 if (!(rdev->flags & RADEON_IS_IGP)) { in cayman_gpu_soft_reset()
1919 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in cayman_gpu_soft_reset()
1933 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in cayman_gpu_soft_reset()
1947 evergreen_mc_resume(rdev, &save); in cayman_gpu_soft_reset()
1950 evergreen_print_gpu_status_regs(rdev); in cayman_gpu_soft_reset()
1953 int cayman_asic_reset(struct radeon_device *rdev, bool hard) in cayman_asic_reset() argument
1958 evergreen_gpu_pci_config_reset(rdev); in cayman_asic_reset()
1962 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_asic_reset()
1965 r600_set_bios_scratch_engine_hung(rdev, true); in cayman_asic_reset()
1967 cayman_gpu_soft_reset(rdev, reset_mask); in cayman_asic_reset()
1969 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_asic_reset()
1972 evergreen_gpu_pci_config_reset(rdev); in cayman_asic_reset()
1974 r600_set_bios_scratch_engine_hung(rdev, false); in cayman_asic_reset()
1988 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in cayman_gfx_is_lockup() argument
1990 u32 reset_mask = cayman_gpu_check_soft_reset(rdev); in cayman_gfx_is_lockup()
1995 radeon_ring_lockup_update(rdev, ring); in cayman_gfx_is_lockup()
1998 return radeon_ring_test_lockup(rdev, ring); in cayman_gfx_is_lockup()
2001 static void cayman_uvd_init(struct radeon_device *rdev) in cayman_uvd_init() argument
2005 if (!rdev->has_uvd) in cayman_uvd_init()
2008 r = radeon_uvd_init(rdev); in cayman_uvd_init()
2010 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); in cayman_uvd_init()
2017 rdev->has_uvd = 0; in cayman_uvd_init()
2020 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in cayman_uvd_init()
2021 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in cayman_uvd_init()
2024 static void cayman_uvd_start(struct radeon_device *rdev) in cayman_uvd_start() argument
2028 if (!rdev->has_uvd) in cayman_uvd_start()
2031 r = uvd_v2_2_resume(rdev); in cayman_uvd_start()
2033 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); in cayman_uvd_start()
2036 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); in cayman_uvd_start()
2038 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in cayman_uvd_start()
2044 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in cayman_uvd_start()
2047 static void cayman_uvd_resume(struct radeon_device *rdev) in cayman_uvd_resume() argument
2052 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) in cayman_uvd_resume()
2055 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in cayman_uvd_resume()
2056 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in cayman_uvd_resume()
2058 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); in cayman_uvd_resume()
2061 r = uvd_v1_0_init(rdev); in cayman_uvd_resume()
2063 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); in cayman_uvd_resume()
2068 static void cayman_vce_init(struct radeon_device *rdev) in cayman_vce_init() argument
2073 if (!rdev->has_vce) in cayman_vce_init()
2076 r = radeon_vce_init(rdev); in cayman_vce_init()
2078 dev_err(rdev->dev, "failed VCE (%d) init.\n", r); in cayman_vce_init()
2085 rdev->has_vce = 0; in cayman_vce_init()
2088 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL; in cayman_vce_init()
2089 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096); in cayman_vce_init()
2090 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL; in cayman_vce_init()
2091 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096); in cayman_vce_init()
2094 static void cayman_vce_start(struct radeon_device *rdev) in cayman_vce_start() argument
2098 if (!rdev->has_vce) in cayman_vce_start()
2101 r = radeon_vce_resume(rdev); in cayman_vce_start()
2103 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); in cayman_vce_start()
2106 r = vce_v1_0_resume(rdev); in cayman_vce_start()
2108 dev_err(rdev->dev, "failed VCE resume (%d).\n", r); in cayman_vce_start()
2111 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX); in cayman_vce_start()
2113 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r); in cayman_vce_start()
2116 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX); in cayman_vce_start()
2118 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r); in cayman_vce_start()
2124 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0; in cayman_vce_start()
2125 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0; in cayman_vce_start()
2128 static void cayman_vce_resume(struct radeon_device *rdev) in cayman_vce_resume() argument
2133 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size) in cayman_vce_resume()
2136 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX]; in cayman_vce_resume()
2137 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_vce_resume()
2139 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); in cayman_vce_resume()
2142 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX]; in cayman_vce_resume()
2143 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0); in cayman_vce_resume()
2145 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r); in cayman_vce_resume()
2148 r = vce_v1_0_init(rdev); in cayman_vce_resume()
2150 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r); in cayman_vce_resume()
2155 static int cayman_startup(struct radeon_device *rdev) in cayman_startup() argument
2157 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_startup()
2161 evergreen_pcie_gen2_enable(rdev); in cayman_startup()
2163 evergreen_program_aspm(rdev); in cayman_startup()
2166 r = r600_vram_scratch_init(rdev); in cayman_startup()
2170 evergreen_mc_program(rdev); in cayman_startup()
2172 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) { in cayman_startup()
2173 r = ni_mc_load_microcode(rdev); in cayman_startup()
2180 r = cayman_pcie_gart_enable(rdev); in cayman_startup()
2183 cayman_gpu_init(rdev); in cayman_startup()
2186 if (rdev->flags & RADEON_IS_IGP) { in cayman_startup()
2187 rdev->rlc.reg_list = tn_rlc_save_restore_register_list; in cayman_startup()
2188 rdev->rlc.reg_list_size = in cayman_startup()
2190 rdev->rlc.cs_data = cayman_cs_data; in cayman_startup()
2191 r = sumo_rlc_init(rdev); in cayman_startup()
2199 r = radeon_wb_init(rdev); in cayman_startup()
2203 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in cayman_startup()
2205 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2209 cayman_uvd_start(rdev); in cayman_startup()
2210 cayman_vce_start(rdev); in cayman_startup()
2212 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX); in cayman_startup()
2214 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2218 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX); in cayman_startup()
2220 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in cayman_startup()
2224 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); in cayman_startup()
2226 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in cayman_startup()
2230 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); in cayman_startup()
2232 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in cayman_startup()
2237 if (!rdev->irq.installed) { in cayman_startup()
2238 r = radeon_irq_kms_init(rdev); in cayman_startup()
2243 r = r600_irq_init(rdev); in cayman_startup()
2246 radeon_irq_kms_fini(rdev); in cayman_startup()
2249 evergreen_irq_set(rdev); in cayman_startup()
2251 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in cayman_startup()
2256 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_startup()
2257 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in cayman_startup()
2262 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_startup()
2263 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET, in cayman_startup()
2268 r = cayman_cp_load_microcode(rdev); in cayman_startup()
2271 r = cayman_cp_resume(rdev); in cayman_startup()
2275 r = cayman_dma_resume(rdev); in cayman_startup()
2279 cayman_uvd_resume(rdev); in cayman_startup()
2280 cayman_vce_resume(rdev); in cayman_startup()
2282 r = radeon_ib_pool_init(rdev); in cayman_startup()
2284 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in cayman_startup()
2288 r = radeon_vm_manager_init(rdev); in cayman_startup()
2290 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r); in cayman_startup()
2294 r = radeon_audio_init(rdev); in cayman_startup()
2301 int cayman_resume(struct radeon_device *rdev) in cayman_resume() argument
2310 atom_asic_init(rdev->mode_info.atom_context); in cayman_resume()
2313 ni_init_golden_registers(rdev); in cayman_resume()
2315 if (rdev->pm.pm_method == PM_METHOD_DPM) in cayman_resume()
2316 radeon_pm_resume(rdev); in cayman_resume()
2318 rdev->accel_working = true; in cayman_resume()
2319 r = cayman_startup(rdev); in cayman_resume()
2322 rdev->accel_working = false; in cayman_resume()
2328 int cayman_suspend(struct radeon_device *rdev) in cayman_suspend() argument
2330 radeon_pm_suspend(rdev); in cayman_suspend()
2331 radeon_audio_fini(rdev); in cayman_suspend()
2332 radeon_vm_manager_fini(rdev); in cayman_suspend()
2333 cayman_cp_enable(rdev, false); in cayman_suspend()
2334 cayman_dma_stop(rdev); in cayman_suspend()
2335 if (rdev->has_uvd) { in cayman_suspend()
2336 uvd_v1_0_fini(rdev); in cayman_suspend()
2337 radeon_uvd_suspend(rdev); in cayman_suspend()
2339 evergreen_irq_suspend(rdev); in cayman_suspend()
2340 radeon_wb_disable(rdev); in cayman_suspend()
2341 cayman_pcie_gart_disable(rdev); in cayman_suspend()
2351 int cayman_init(struct radeon_device *rdev) in cayman_init() argument
2353 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in cayman_init()
2357 if (!radeon_get_bios(rdev)) { in cayman_init()
2358 if (ASIC_IS_AVIVO(rdev)) in cayman_init()
2362 if (!rdev->is_atom_bios) { in cayman_init()
2363 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n"); in cayman_init()
2366 r = radeon_atombios_init(rdev); in cayman_init()
2371 if (!radeon_card_posted(rdev)) { in cayman_init()
2372 if (!rdev->bios) { in cayman_init()
2373 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in cayman_init()
2377 atom_asic_init(rdev->mode_info.atom_context); in cayman_init()
2380 ni_init_golden_registers(rdev); in cayman_init()
2382 r600_scratch_init(rdev); in cayman_init()
2384 radeon_surface_init(rdev); in cayman_init()
2386 radeon_get_clock_info(rdev->ddev); in cayman_init()
2388 r = radeon_fence_driver_init(rdev); in cayman_init()
2392 r = evergreen_mc_init(rdev); in cayman_init()
2396 r = radeon_bo_init(rdev); in cayman_init()
2400 if (rdev->flags & RADEON_IS_IGP) { in cayman_init()
2401 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in cayman_init()
2402 r = ni_init_microcode(rdev); in cayman_init()
2409 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { in cayman_init()
2410 r = ni_init_microcode(rdev); in cayman_init()
2419 radeon_pm_init(rdev); in cayman_init()
2422 r600_ring_init(rdev, ring, 1024 * 1024); in cayman_init()
2424 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in cayman_init()
2426 r600_ring_init(rdev, ring, 64 * 1024); in cayman_init()
2428 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; in cayman_init()
2430 r600_ring_init(rdev, ring, 64 * 1024); in cayman_init()
2432 cayman_uvd_init(rdev); in cayman_init()
2433 cayman_vce_init(rdev); in cayman_init()
2435 rdev->ih.ring_obj = NULL; in cayman_init()
2436 r600_ih_ring_init(rdev, 64 * 1024); in cayman_init()
2438 r = r600_pcie_gart_init(rdev); in cayman_init()
2442 rdev->accel_working = true; in cayman_init()
2443 r = cayman_startup(rdev); in cayman_init()
2445 dev_err(rdev->dev, "disabling GPU acceleration\n"); in cayman_init()
2446 cayman_cp_fini(rdev); in cayman_init()
2447 cayman_dma_fini(rdev); in cayman_init()
2448 r600_irq_fini(rdev); in cayman_init()
2449 if (rdev->flags & RADEON_IS_IGP) in cayman_init()
2450 sumo_rlc_fini(rdev); in cayman_init()
2451 radeon_wb_fini(rdev); in cayman_init()
2452 radeon_ib_pool_fini(rdev); in cayman_init()
2453 radeon_vm_manager_fini(rdev); in cayman_init()
2454 radeon_irq_kms_fini(rdev); in cayman_init()
2455 cayman_pcie_gart_fini(rdev); in cayman_init()
2456 rdev->accel_working = false; in cayman_init()
2466 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { in cayman_init()
2474 void cayman_fini(struct radeon_device *rdev) in cayman_fini() argument
2476 radeon_pm_fini(rdev); in cayman_fini()
2477 cayman_cp_fini(rdev); in cayman_fini()
2478 cayman_dma_fini(rdev); in cayman_fini()
2479 r600_irq_fini(rdev); in cayman_fini()
2480 if (rdev->flags & RADEON_IS_IGP) in cayman_fini()
2481 sumo_rlc_fini(rdev); in cayman_fini()
2482 radeon_wb_fini(rdev); in cayman_fini()
2483 radeon_vm_manager_fini(rdev); in cayman_fini()
2484 radeon_ib_pool_fini(rdev); in cayman_fini()
2485 radeon_irq_kms_fini(rdev); in cayman_fini()
2486 uvd_v1_0_fini(rdev); in cayman_fini()
2487 radeon_uvd_fini(rdev); in cayman_fini()
2488 if (rdev->has_vce) in cayman_fini()
2489 radeon_vce_fini(rdev); in cayman_fini()
2490 cayman_pcie_gart_fini(rdev); in cayman_fini()
2491 r600_vram_scratch_fini(rdev); in cayman_fini()
2492 radeon_gem_fini(rdev); in cayman_fini()
2493 radeon_fence_driver_fini(rdev); in cayman_fini()
2494 radeon_bo_fini(rdev); in cayman_fini()
2495 radeon_atombios_fini(rdev); in cayman_fini()
2496 kfree(rdev->bios); in cayman_fini()
2497 rdev->bios = NULL; in cayman_fini()
2503 int cayman_vm_init(struct radeon_device *rdev) in cayman_vm_init() argument
2506 rdev->vm_manager.nvm = 8; in cayman_vm_init()
2508 if (rdev->flags & RADEON_IS_IGP) { in cayman_vm_init()
2511 rdev->vm_manager.vram_base_offset = tmp; in cayman_vm_init()
2513 rdev->vm_manager.vram_base_offset = 0; in cayman_vm_init()
2517 void cayman_vm_fini(struct radeon_device *rdev) in cayman_vm_fini() argument
2530 void cayman_vm_decode_fault(struct radeon_device *rdev, in cayman_vm_decode_fault() argument
2690 void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, in cayman_vm_flush() argument
2719 int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) in tn_set_vce_clocks() argument
2724 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in tn_set_vce_clocks()