3824 	u32 reset_mask = 0;  in evergreen_gpu_check_soft_reset()  local
3834 		reset_mask |= RADEON_RESET_GFX;  in evergreen_gpu_check_soft_reset()
3838 		reset_mask |= RADEON_RESET_CP;  in evergreen_gpu_check_soft_reset()
3841 		reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;  in evergreen_gpu_check_soft_reset()
3846 		reset_mask |= RADEON_RESET_DMA;  in evergreen_gpu_check_soft_reset()
3851 		reset_mask |= RADEON_RESET_DMA;  in evergreen_gpu_check_soft_reset()
3856 		reset_mask |= RADEON_RESET_RLC;  in evergreen_gpu_check_soft_reset()
3859 		reset_mask |= RADEON_RESET_IH;  in evergreen_gpu_check_soft_reset()
3862 		reset_mask |= RADEON_RESET_SEM;  in evergreen_gpu_check_soft_reset()
3865 		reset_mask |= RADEON_RESET_GRBM;  in evergreen_gpu_check_soft_reset()
3868 		reset_mask |= RADEON_RESET_VMC;  in evergreen_gpu_check_soft_reset()
3872 		reset_mask |= RADEON_RESET_MC;  in evergreen_gpu_check_soft_reset()
3875 		reset_mask |= RADEON_RESET_DISPLAY;  in evergreen_gpu_check_soft_reset()
3880 		reset_mask |= RADEON_RESET_VMC;  in evergreen_gpu_check_soft_reset()
3883 	if (reset_mask & RADEON_RESET_MC) {  in evergreen_gpu_check_soft_reset()
3884 		DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);  in evergreen_gpu_check_soft_reset()
3885 		reset_mask &= ~RADEON_RESET_MC;  in evergreen_gpu_check_soft_reset()
3888 	return reset_mask;  in evergreen_gpu_check_soft_reset()
3891 static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)  in evergreen_gpu_soft_reset()  argument
3897 	if (reset_mask == 0)  in evergreen_gpu_soft_reset()
3900 	dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);  in evergreen_gpu_soft_reset()
3907 	if (reset_mask & RADEON_RESET_DMA) {  in evergreen_gpu_soft_reset()
3921 	if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {  in evergreen_gpu_soft_reset()
3935 	if (reset_mask & RADEON_RESET_CP) {  in evergreen_gpu_soft_reset()
3942 	if (reset_mask & RADEON_RESET_DMA)  in evergreen_gpu_soft_reset()
3945 	if (reset_mask & RADEON_RESET_DISPLAY)  in evergreen_gpu_soft_reset()
3948 	if (reset_mask & RADEON_RESET_RLC)  in evergreen_gpu_soft_reset()
3951 	if (reset_mask & RADEON_RESET_SEM)  in evergreen_gpu_soft_reset()
3954 	if (reset_mask & RADEON_RESET_IH)  in evergreen_gpu_soft_reset()
3957 	if (reset_mask & RADEON_RESET_GRBM)  in evergreen_gpu_soft_reset()
3960 	if (reset_mask & RADEON_RESET_VMC)  in evergreen_gpu_soft_reset()
3964 		if (reset_mask & RADEON_RESET_MC)  in evergreen_gpu_soft_reset()
4049 	u32 reset_mask;  in evergreen_asic_reset()  local
4056 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4058 	if (reset_mask)  in evergreen_asic_reset()
4062 	evergreen_gpu_soft_reset(rdev, reset_mask);  in evergreen_asic_reset()
4064 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4067 	if (reset_mask && radeon_hard_reset)  in evergreen_asic_reset()
4070 	reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_asic_reset()
4072 	if (!reset_mask)  in evergreen_asic_reset()
4089 	u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);  in evergreen_gfx_is_lockup()  local
4091 	if (!(reset_mask & (RADEON_RESET_GFX |  in evergreen_gfx_is_lockup()