Lines Matching refs:rdev
45 u32 eg_cg_rreg(struct radeon_device *rdev, u32 reg) in eg_cg_rreg() argument
50 spin_lock_irqsave(&rdev->cg_idx_lock, flags); in eg_cg_rreg()
53 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); in eg_cg_rreg()
57 void eg_cg_wreg(struct radeon_device *rdev, u32 reg, u32 v) in eg_cg_wreg() argument
61 spin_lock_irqsave(&rdev->cg_idx_lock, flags); in eg_cg_wreg()
64 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); in eg_cg_wreg()
67 u32 eg_pif_phy0_rreg(struct radeon_device *rdev, u32 reg) in eg_pif_phy0_rreg() argument
72 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy0_rreg()
75 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); in eg_pif_phy0_rreg()
79 void eg_pif_phy0_wreg(struct radeon_device *rdev, u32 reg, u32 v) in eg_pif_phy0_wreg() argument
83 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy0_wreg()
86 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); in eg_pif_phy0_wreg()
89 u32 eg_pif_phy1_rreg(struct radeon_device *rdev, u32 reg) in eg_pif_phy1_rreg() argument
94 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy1_rreg()
97 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); in eg_pif_phy1_rreg()
101 void eg_pif_phy1_wreg(struct radeon_device *rdev, u32 reg, u32 v) in eg_pif_phy1_wreg() argument
105 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy1_wreg()
108 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); in eg_pif_phy1_wreg()
208 static void evergreen_gpu_init(struct radeon_device *rdev);
209 void evergreen_fini(struct radeon_device *rdev);
210 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
211 void evergreen_program_aspm(struct radeon_device *rdev);
212 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
214 extern void cayman_vm_decode_fault(struct radeon_device *rdev,
216 void cik_init_cp_pg_table(struct radeon_device *rdev);
218 extern u32 si_get_csb_size(struct radeon_device *rdev);
219 extern void si_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);
220 extern u32 cik_get_csb_size(struct radeon_device *rdev);
221 extern void cik_get_csb_buffer(struct radeon_device *rdev, volatile u32 *buffer);
222 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
996 static void evergreen_init_golden_registers(struct radeon_device *rdev) in evergreen_init_golden_registers() argument
998 switch (rdev->family) { in evergreen_init_golden_registers()
1001 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1004 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1007 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1012 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1015 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1018 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1023 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1026 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1029 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1034 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1037 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1040 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1045 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1050 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1055 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1058 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1063 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1068 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1073 radeon_program_register_sequence(rdev, in evergreen_init_golden_registers()
1092 int evergreen_get_allowed_info_register(struct radeon_device *rdev, in evergreen_get_allowed_info_register() argument
1141 static int sumo_set_uvd_clock(struct radeon_device *rdev, u32 clock, in sumo_set_uvd_clock() argument
1147 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, in sumo_set_uvd_clock()
1165 int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in sumo_set_uvd_clocks() argument
1170 r = sumo_set_uvd_clock(rdev, vclk, CG_VCLK_CNTL, CG_VCLK_STATUS); in sumo_set_uvd_clocks()
1176 r = sumo_set_uvd_clock(rdev, dclk, CG_DCLK_CNTL, CG_DCLK_STATUS); in sumo_set_uvd_clocks()
1188 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) in evergreen_set_uvd_clocks() argument
1208 r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 125000, 250000, in evergreen_set_uvd_clocks()
1226 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in evergreen_set_uvd_clocks()
1263 r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL); in evergreen_set_uvd_clocks()
1277 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) in evergreen_fix_pci_max_read_req_size() argument
1282 readrq = pcie_get_readrq(rdev->pdev); in evergreen_fix_pci_max_read_req_size()
1288 pcie_set_readrq(rdev->pdev, 512); in evergreen_fix_pci_max_read_req_size()
1294 struct radeon_device *rdev = dev->dev_private; in dce4_program_fmt() local
1347 static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc) in dce4_is_in_vblank() argument
1355 static bool dce4_is_counter_moving(struct radeon_device *rdev, int crtc) in dce4_is_counter_moving() argument
1376 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc) in dce4_wait_for_vblank() argument
1380 if (crtc >= rdev->num_crtc) in dce4_wait_for_vblank()
1389 while (dce4_is_in_vblank(rdev, crtc)) { in dce4_wait_for_vblank()
1391 if (!dce4_is_counter_moving(rdev, crtc)) in dce4_wait_for_vblank()
1396 while (!dce4_is_in_vblank(rdev, crtc)) { in dce4_wait_for_vblank()
1398 if (!dce4_is_counter_moving(rdev, crtc)) in dce4_wait_for_vblank()
1414 void evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, in evergreen_page_flip() argument
1417 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip()
1438 bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc_id) in evergreen_page_flip_pending() argument
1440 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in evergreen_page_flip_pending()
1448 int evergreen_get_temp(struct radeon_device *rdev) in evergreen_get_temp() argument
1453 if (rdev->family == CHIP_JUNIPER) { in evergreen_get_temp()
1486 int sumo_get_temp(struct radeon_device *rdev) in sumo_get_temp() argument
1503 void sumo_pm_init_profile(struct radeon_device *rdev) in sumo_pm_init_profile() argument
1508 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in sumo_pm_init_profile()
1509 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in sumo_pm_init_profile()
1510 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1511 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1514 if (rdev->flags & RADEON_IS_MOBILITY) in sumo_pm_init_profile()
1515 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); in sumo_pm_init_profile()
1517 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in sumo_pm_init_profile()
1519 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1520 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1521 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1522 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1524 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1525 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1526 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1527 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1529 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1530 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1531 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1532 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1534 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1535 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1536 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1537 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in sumo_pm_init_profile()
1540 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in sumo_pm_init_profile()
1541 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1542 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1543 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1544 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = in sumo_pm_init_profile()
1545 rdev->pm.power_state[idx].num_clock_modes - 1; in sumo_pm_init_profile()
1547 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; in sumo_pm_init_profile()
1548 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; in sumo_pm_init_profile()
1549 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in sumo_pm_init_profile()
1550 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = in sumo_pm_init_profile()
1551 rdev->pm.power_state[idx].num_clock_modes - 1; in sumo_pm_init_profile()
1563 void btc_pm_init_profile(struct radeon_device *rdev) in btc_pm_init_profile() argument
1568 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in btc_pm_init_profile()
1569 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in btc_pm_init_profile()
1570 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1571 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2; in btc_pm_init_profile()
1576 if (rdev->flags & RADEON_IS_MOBILITY) in btc_pm_init_profile()
1577 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0); in btc_pm_init_profile()
1579 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0); in btc_pm_init_profile()
1581 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1582 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1583 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1584 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in btc_pm_init_profile()
1586 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1587 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1588 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1589 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1; in btc_pm_init_profile()
1591 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1592 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1593 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1594 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2; in btc_pm_init_profile()
1596 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1597 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1598 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1599 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in btc_pm_init_profile()
1601 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1602 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1603 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1604 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1; in btc_pm_init_profile()
1606 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx; in btc_pm_init_profile()
1607 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx; in btc_pm_init_profile()
1608 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in btc_pm_init_profile()
1609 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2; in btc_pm_init_profile()
1620 void evergreen_pm_misc(struct radeon_device *rdev) in evergreen_pm_misc() argument
1622 int req_ps_idx = rdev->pm.requested_power_state_index; in evergreen_pm_misc()
1623 int req_cm_idx = rdev->pm.requested_clock_mode_index; in evergreen_pm_misc()
1624 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx]; in evergreen_pm_misc()
1631 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) { in evergreen_pm_misc()
1632 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC); in evergreen_pm_misc()
1633 rdev->pm.current_vddc = voltage->voltage; in evergreen_pm_misc()
1641 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && in evergreen_pm_misc()
1642 (rdev->family >= CHIP_BARTS) && in evergreen_pm_misc()
1643 rdev->pm.active_crtc_count && in evergreen_pm_misc()
1644 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || in evergreen_pm_misc()
1645 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) in evergreen_pm_misc()
1646 voltage = &rdev->pm.power_state[req_ps_idx]. in evergreen_pm_misc()
1647 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].voltage; in evergreen_pm_misc()
1652 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) { in evergreen_pm_misc()
1653 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI); in evergreen_pm_misc()
1654 rdev->pm.current_vddci = voltage->vddci; in evergreen_pm_misc()
1667 void evergreen_pm_prepare(struct radeon_device *rdev) in evergreen_pm_prepare() argument
1669 struct drm_device *ddev = rdev->ddev; in evergreen_pm_prepare()
1692 void evergreen_pm_finish(struct radeon_device *rdev) in evergreen_pm_finish() argument
1694 struct drm_device *ddev = rdev->ddev; in evergreen_pm_finish()
1719 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) in evergreen_hpd_sense() argument
1735 void evergreen_hpd_set_polarity(struct radeon_device *rdev, in evergreen_hpd_set_polarity() argument
1738 bool connected = evergreen_hpd_sense(rdev, hpd); in evergreen_hpd_set_polarity()
1757 void evergreen_hpd_init(struct radeon_device *rdev) in evergreen_hpd_init() argument
1759 struct drm_device *dev = rdev->ddev; in evergreen_hpd_init()
1785 radeon_hpd_set_polarity(rdev, hpd); in evergreen_hpd_init()
1787 radeon_irq_kms_enable_hpd(rdev, enabled); in evergreen_hpd_init()
1798 void evergreen_hpd_fini(struct radeon_device *rdev) in evergreen_hpd_fini() argument
1800 struct drm_device *dev = rdev->ddev; in evergreen_hpd_fini()
1814 radeon_irq_kms_disable_hpd(rdev, disabled); in evergreen_hpd_fini()
1819 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, in evergreen_line_buffer_adjust() argument
1865 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) { in evergreen_line_buffer_adjust()
1868 for (i = 0; i < rdev->usec_timeout; i++) { in evergreen_line_buffer_adjust()
1881 if (ASIC_IS_DCE5(rdev)) in evergreen_line_buffer_adjust()
1887 if (ASIC_IS_DCE5(rdev)) in evergreen_line_buffer_adjust()
1893 if (ASIC_IS_DCE5(rdev)) in evergreen_line_buffer_adjust()
1899 if (ASIC_IS_DCE5(rdev)) in evergreen_line_buffer_adjust()
1910 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev) in evergreen_get_number_of_dram_channels() argument
2148 static void evergreen_program_watermarks(struct radeon_device *rdev, in evergreen_program_watermarks() argument
2173 dram_channels = evergreen_get_number_of_dram_channels(rdev); in evergreen_program_watermarks()
2176 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in evergreen_program_watermarks()
2178 radeon_dpm_get_mclk(rdev, false) * 10; in evergreen_program_watermarks()
2180 radeon_dpm_get_sclk(rdev, false) * 10; in evergreen_program_watermarks()
2182 wm_high.yclk = rdev->pm.current_mclk * 10; in evergreen_program_watermarks()
2183 wm_high.sclk = rdev->pm.current_sclk * 10; in evergreen_program_watermarks()
2203 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { in evergreen_program_watermarks()
2205 radeon_dpm_get_mclk(rdev, true) * 10; in evergreen_program_watermarks()
2207 radeon_dpm_get_sclk(rdev, true) * 10; in evergreen_program_watermarks()
2209 wm_low.yclk = rdev->pm.current_mclk * 10; in evergreen_program_watermarks()
2210 wm_low.sclk = rdev->pm.current_sclk * 10; in evergreen_program_watermarks()
2239 (rdev->disp_priority == 2)) { in evergreen_program_watermarks()
2246 (rdev->disp_priority == 2)) { in evergreen_program_watermarks()
2317 void evergreen_bandwidth_update(struct radeon_device *rdev) in evergreen_bandwidth_update() argument
2324 if (!rdev->mode_info.mode_config_initialized) in evergreen_bandwidth_update()
2327 radeon_update_display_priority(rdev); in evergreen_bandwidth_update()
2329 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_bandwidth_update()
2330 if (rdev->mode_info.crtcs[i]->base.enabled) in evergreen_bandwidth_update()
2333 for (i = 0; i < rdev->num_crtc; i += 2) { in evergreen_bandwidth_update()
2334 mode0 = &rdev->mode_info.crtcs[i]->base.mode; in evergreen_bandwidth_update()
2335 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode; in evergreen_bandwidth_update()
2336 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1); in evergreen_bandwidth_update()
2337 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads); in evergreen_bandwidth_update()
2338 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0); in evergreen_bandwidth_update()
2339 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads); in evergreen_bandwidth_update()
2352 int evergreen_mc_wait_for_idle(struct radeon_device *rdev) in evergreen_mc_wait_for_idle() argument
2357 for (i = 0; i < rdev->usec_timeout; i++) { in evergreen_mc_wait_for_idle()
2370 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev) in evergreen_pcie_gart_tlb_flush() argument
2378 for (i = 0; i < rdev->usec_timeout; i++) { in evergreen_pcie_gart_tlb_flush()
2393 static int evergreen_pcie_gart_enable(struct radeon_device *rdev) in evergreen_pcie_gart_enable() argument
2398 if (rdev->gart.robj == NULL) { in evergreen_pcie_gart_enable()
2399 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in evergreen_pcie_gart_enable()
2402 r = radeon_gart_table_vram_pin(rdev); in evergreen_pcie_gart_enable()
2416 if (rdev->flags & RADEON_IS_IGP) { in evergreen_pcie_gart_enable()
2424 if ((rdev->family == CHIP_JUNIPER) || in evergreen_pcie_gart_enable()
2425 (rdev->family == CHIP_CYPRESS) || in evergreen_pcie_gart_enable()
2426 (rdev->family == CHIP_HEMLOCK) || in evergreen_pcie_gart_enable()
2427 (rdev->family == CHIP_BARTS)) in evergreen_pcie_gart_enable()
2434 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); in evergreen_pcie_gart_enable()
2435 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); in evergreen_pcie_gart_enable()
2436 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); in evergreen_pcie_gart_enable()
2440 (u32)(rdev->dummy_page.addr >> 12)); in evergreen_pcie_gart_enable()
2443 evergreen_pcie_gart_tlb_flush(rdev); in evergreen_pcie_gart_enable()
2445 (unsigned)(rdev->mc.gtt_size >> 20), in evergreen_pcie_gart_enable()
2446 (unsigned long long)rdev->gart.table_addr); in evergreen_pcie_gart_enable()
2447 rdev->gart.ready = true; in evergreen_pcie_gart_enable()
2451 static void evergreen_pcie_gart_disable(struct radeon_device *rdev) in evergreen_pcie_gart_disable() argument
2473 radeon_gart_table_vram_unpin(rdev); in evergreen_pcie_gart_disable()
2476 static void evergreen_pcie_gart_fini(struct radeon_device *rdev) in evergreen_pcie_gart_fini() argument
2478 evergreen_pcie_gart_disable(rdev); in evergreen_pcie_gart_fini()
2479 radeon_gart_table_vram_free(rdev); in evergreen_pcie_gart_fini()
2480 radeon_gart_fini(rdev); in evergreen_pcie_gart_fini()
2484 static void evergreen_agp_enable(struct radeon_device *rdev) in evergreen_agp_enable() argument
2560 static bool evergreen_is_dp_sst_stream_enabled(struct radeon_device *rdev, in evergreen_is_dp_sst_stream_enabled() argument
2620 static void evergreen_blank_dp_output(struct radeon_device *rdev, in evergreen_blank_dp_output() argument
2660 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) in evergreen_mc_stop() argument
2666 if (!ASIC_IS_NODCE(rdev)) { in evergreen_mc_stop()
2674 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_stop()
2678 if (ASIC_IS_DCE6(rdev)) { in evergreen_mc_stop()
2681 radeon_wait_for_vblank(rdev, i); in evergreen_mc_stop()
2690 radeon_wait_for_vblank(rdev, i); in evergreen_mc_stop()
2698 frame_count = radeon_get_vblank_counter(rdev, i); in evergreen_mc_stop()
2699 for (j = 0; j < rdev->usec_timeout; j++) { in evergreen_mc_stop()
2700 if (radeon_get_vblank_counter(rdev, i) != frame_count) in evergreen_mc_stop()
2711 if (ASIC_IS_DCE5(rdev) && in evergreen_mc_stop()
2712 evergreen_is_dp_sst_stream_enabled(rdev, i ,&dig_fe)) in evergreen_mc_stop()
2713 evergreen_blank_dp_output(rdev, dig_fe); in evergreen_mc_stop()
2728 radeon_mc_wait_for_idle(rdev); in evergreen_mc_stop()
2742 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_stop()
2758 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) in evergreen_mc_resume() argument
2764 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_resume()
2766 upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2768 upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2770 (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2772 (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2775 if (!ASIC_IS_NODCE(rdev)) { in evergreen_mc_resume()
2776 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); in evergreen_mc_resume()
2777 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); in evergreen_mc_resume()
2781 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_resume()
2798 for (j = 0; j < rdev->usec_timeout; j++) { in evergreen_mc_resume()
2814 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_mc_resume()
2816 if (ASIC_IS_DCE6(rdev)) { in evergreen_mc_resume()
2830 frame_count = radeon_get_vblank_counter(rdev, i); in evergreen_mc_resume()
2831 for (j = 0; j < rdev->usec_timeout; j++) { in evergreen_mc_resume()
2832 if (radeon_get_vblank_counter(rdev, i) != frame_count) in evergreen_mc_resume()
2838 if (!ASIC_IS_NODCE(rdev)) { in evergreen_mc_resume()
2846 void evergreen_mc_program(struct radeon_device *rdev) in evergreen_mc_program() argument
2862 evergreen_mc_stop(rdev, &save); in evergreen_mc_program()
2863 if (evergreen_mc_wait_for_idle(rdev)) { in evergreen_mc_program()
2864 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_mc_program()
2869 if (rdev->flags & RADEON_IS_AGP) { in evergreen_mc_program()
2870 if (rdev->mc.vram_start < rdev->mc.gtt_start) { in evergreen_mc_program()
2873 rdev->mc.vram_start >> 12); in evergreen_mc_program()
2875 rdev->mc.gtt_end >> 12); in evergreen_mc_program()
2879 rdev->mc.gtt_start >> 12); in evergreen_mc_program()
2881 rdev->mc.vram_end >> 12); in evergreen_mc_program()
2885 rdev->mc.vram_start >> 12); in evergreen_mc_program()
2887 rdev->mc.vram_end >> 12); in evergreen_mc_program()
2889 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); in evergreen_mc_program()
2891 if ((rdev->family == CHIP_PALM) || in evergreen_mc_program()
2892 (rdev->family == CHIP_SUMO) || in evergreen_mc_program()
2893 (rdev->family == CHIP_SUMO2)) { in evergreen_mc_program()
2895 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24; in evergreen_mc_program()
2896 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; in evergreen_mc_program()
2899 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; in evergreen_mc_program()
2900 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); in evergreen_mc_program()
2902 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); in evergreen_mc_program()
2905 if (rdev->flags & RADEON_IS_AGP) { in evergreen_mc_program()
2906 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); in evergreen_mc_program()
2907 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); in evergreen_mc_program()
2908 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); in evergreen_mc_program()
2914 if (evergreen_mc_wait_for_idle(rdev)) { in evergreen_mc_program()
2915 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_mc_program()
2917 evergreen_mc_resume(rdev, &save); in evergreen_mc_program()
2920 rv515_vga_render_disable(rdev); in evergreen_mc_program()
2926 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) in evergreen_ring_ib_execute() argument
2928 struct radeon_ring *ring = &rdev->ring[ib->ring]; in evergreen_ring_ib_execute()
2941 } else if (rdev->wb.enabled) { in evergreen_ring_ib_execute()
2961 static int evergreen_cp_load_microcode(struct radeon_device *rdev) in evergreen_cp_load_microcode() argument
2966 if (!rdev->me_fw || !rdev->pfp_fw) in evergreen_cp_load_microcode()
2969 r700_cp_stop(rdev); in evergreen_cp_load_microcode()
2976 fw_data = (const __be32 *)rdev->pfp_fw->data; in evergreen_cp_load_microcode()
2982 fw_data = (const __be32 *)rdev->me_fw->data; in evergreen_cp_load_microcode()
2993 static int evergreen_cp_start(struct radeon_device *rdev) in evergreen_cp_start() argument
2995 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in evergreen_cp_start()
2999 r = radeon_ring_lock(rdev, ring, 7); in evergreen_cp_start()
3007 radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1); in evergreen_cp_start()
3011 radeon_ring_unlock_commit(rdev, ring, false); in evergreen_cp_start()
3016 r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19); in evergreen_cp_start()
3054 radeon_ring_unlock_commit(rdev, ring, false); in evergreen_cp_start()
3059 static int evergreen_cp_resume(struct radeon_device *rdev) in evergreen_cp_resume() argument
3061 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in evergreen_cp_resume()
3099 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC)); in evergreen_cp_resume()
3100 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); in evergreen_cp_resume()
3101 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); in evergreen_cp_resume()
3103 if (rdev->wb.enabled) in evergreen_cp_resume()
3116 evergreen_cp_start(rdev); in evergreen_cp_resume()
3118 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring); in evergreen_cp_resume()
3129 static void evergreen_gpu_init(struct radeon_device *rdev) in evergreen_gpu_init() argument
3150 switch (rdev->family) { in evergreen_gpu_init()
3153 rdev->config.evergreen.num_ses = 2; in evergreen_gpu_init()
3154 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3155 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()
3156 rdev->config.evergreen.max_simds = 10; in evergreen_gpu_init()
3157 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3158 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3159 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3160 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3161 rdev->config.evergreen.max_stack_entries = 512; in evergreen_gpu_init()
3162 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3163 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3164 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3165 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3166 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3167 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3169 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3170 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3171 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3175 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3176 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3177 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3178 rdev->config.evergreen.max_simds = 10; in evergreen_gpu_init()
3179 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3180 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3181 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3182 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3183 rdev->config.evergreen.max_stack_entries = 512; in evergreen_gpu_init()
3184 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3185 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3186 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3187 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3188 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3189 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3191 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3192 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3193 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3197 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3198 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3199 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3200 rdev->config.evergreen.max_simds = 5; in evergreen_gpu_init()
3201 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3202 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3203 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3204 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3205 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3206 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3207 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3208 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3209 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3210 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3211 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3213 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3214 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3215 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3220 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3221 rdev->config.evergreen.max_pipes = 2; in evergreen_gpu_init()
3222 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()
3223 rdev->config.evergreen.max_simds = 2; in evergreen_gpu_init()
3224 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3225 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3226 rdev->config.evergreen.max_threads = 192; in evergreen_gpu_init()
3227 rdev->config.evergreen.max_gs_threads = 16; in evergreen_gpu_init()
3228 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3229 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3230 rdev->config.evergreen.sx_max_export_size = 128; in evergreen_gpu_init()
3231 rdev->config.evergreen.sx_max_export_pos_size = 32; in evergreen_gpu_init()
3232 rdev->config.evergreen.sx_max_export_smx_size = 96; in evergreen_gpu_init()
3233 rdev->config.evergreen.max_hw_contexts = 4; in evergreen_gpu_init()
3234 rdev->config.evergreen.sq_num_cf_insts = 1; in evergreen_gpu_init()
3236 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3237 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3238 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3242 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3243 rdev->config.evergreen.max_pipes = 2; in evergreen_gpu_init()
3244 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()
3245 rdev->config.evergreen.max_simds = 2; in evergreen_gpu_init()
3246 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3247 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3248 rdev->config.evergreen.max_threads = 192; in evergreen_gpu_init()
3249 rdev->config.evergreen.max_gs_threads = 16; in evergreen_gpu_init()
3250 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3251 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3252 rdev->config.evergreen.sx_max_export_size = 128; in evergreen_gpu_init()
3253 rdev->config.evergreen.sx_max_export_pos_size = 32; in evergreen_gpu_init()
3254 rdev->config.evergreen.sx_max_export_smx_size = 96; in evergreen_gpu_init()
3255 rdev->config.evergreen.max_hw_contexts = 4; in evergreen_gpu_init()
3256 rdev->config.evergreen.sq_num_cf_insts = 1; in evergreen_gpu_init()
3258 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3259 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3260 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3264 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3265 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3266 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3267 if (rdev->pdev->device == 0x9648) in evergreen_gpu_init()
3268 rdev->config.evergreen.max_simds = 3; in evergreen_gpu_init()
3269 else if ((rdev->pdev->device == 0x9647) || in evergreen_gpu_init()
3270 (rdev->pdev->device == 0x964a)) in evergreen_gpu_init()
3271 rdev->config.evergreen.max_simds = 4; in evergreen_gpu_init()
3273 rdev->config.evergreen.max_simds = 5; in evergreen_gpu_init()
3274 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3275 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3276 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3277 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3278 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3279 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3280 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3281 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3282 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3283 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3284 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3286 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3287 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3288 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3292 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3293 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3294 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3295 rdev->config.evergreen.max_simds = 2; in evergreen_gpu_init()
3296 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3297 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3298 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3299 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3300 rdev->config.evergreen.max_stack_entries = 512; in evergreen_gpu_init()
3301 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3302 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3303 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3304 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3305 rdev->config.evergreen.max_hw_contexts = 4; in evergreen_gpu_init()
3306 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3308 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3309 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3310 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3314 rdev->config.evergreen.num_ses = 2; in evergreen_gpu_init()
3315 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3316 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()
3317 rdev->config.evergreen.max_simds = 7; in evergreen_gpu_init()
3318 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3319 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3320 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3321 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3322 rdev->config.evergreen.max_stack_entries = 512; in evergreen_gpu_init()
3323 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3324 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3325 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3326 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3327 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3328 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3330 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3331 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3332 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3336 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3337 rdev->config.evergreen.max_pipes = 4; in evergreen_gpu_init()
3338 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()
3339 rdev->config.evergreen.max_simds = 6; in evergreen_gpu_init()
3340 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3341 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3342 rdev->config.evergreen.max_threads = 248; in evergreen_gpu_init()
3343 rdev->config.evergreen.max_gs_threads = 32; in evergreen_gpu_init()
3344 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3345 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3346 rdev->config.evergreen.sx_max_export_size = 256; in evergreen_gpu_init()
3347 rdev->config.evergreen.sx_max_export_pos_size = 64; in evergreen_gpu_init()
3348 rdev->config.evergreen.sx_max_export_smx_size = 192; in evergreen_gpu_init()
3349 rdev->config.evergreen.max_hw_contexts = 8; in evergreen_gpu_init()
3350 rdev->config.evergreen.sq_num_cf_insts = 2; in evergreen_gpu_init()
3352 rdev->config.evergreen.sc_prim_fifo_size = 0x100; in evergreen_gpu_init()
3353 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3354 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3358 rdev->config.evergreen.num_ses = 1; in evergreen_gpu_init()
3359 rdev->config.evergreen.max_pipes = 2; in evergreen_gpu_init()
3360 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()
3361 rdev->config.evergreen.max_simds = 2; in evergreen_gpu_init()
3362 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; in evergreen_gpu_init()
3363 rdev->config.evergreen.max_gprs = 256; in evergreen_gpu_init()
3364 rdev->config.evergreen.max_threads = 192; in evergreen_gpu_init()
3365 rdev->config.evergreen.max_gs_threads = 16; in evergreen_gpu_init()
3366 rdev->config.evergreen.max_stack_entries = 256; in evergreen_gpu_init()
3367 rdev->config.evergreen.sx_num_of_sets = 4; in evergreen_gpu_init()
3368 rdev->config.evergreen.sx_max_export_size = 128; in evergreen_gpu_init()
3369 rdev->config.evergreen.sx_max_export_pos_size = 32; in evergreen_gpu_init()
3370 rdev->config.evergreen.sx_max_export_smx_size = 96; in evergreen_gpu_init()
3371 rdev->config.evergreen.max_hw_contexts = 4; in evergreen_gpu_init()
3372 rdev->config.evergreen.sq_num_cf_insts = 1; in evergreen_gpu_init()
3374 rdev->config.evergreen.sc_prim_fifo_size = 0x40; in evergreen_gpu_init()
3375 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; in evergreen_gpu_init()
3376 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; in evergreen_gpu_init()
3394 evergreen_fix_pci_max_read_req_size(rdev); in evergreen_gpu_init()
3397 if ((rdev->family == CHIP_PALM) || in evergreen_gpu_init()
3398 (rdev->family == CHIP_SUMO) || in evergreen_gpu_init()
3399 (rdev->family == CHIP_SUMO2)) in evergreen_gpu_init()
3411 rdev->config.evergreen.tile_config = 0; in evergreen_gpu_init()
3412 switch (rdev->config.evergreen.max_tile_pipes) { in evergreen_gpu_init()
3415 rdev->config.evergreen.tile_config |= (0 << 0); in evergreen_gpu_init()
3418 rdev->config.evergreen.tile_config |= (1 << 0); in evergreen_gpu_init()
3421 rdev->config.evergreen.tile_config |= (2 << 0); in evergreen_gpu_init()
3424 rdev->config.evergreen.tile_config |= (3 << 0); in evergreen_gpu_init()
3428 if (rdev->flags & RADEON_IS_IGP) in evergreen_gpu_init()
3429 rdev->config.evergreen.tile_config |= 1 << 4; in evergreen_gpu_init()
3433 rdev->config.evergreen.tile_config |= 0 << 4; in evergreen_gpu_init()
3436 rdev->config.evergreen.tile_config |= 1 << 4; in evergreen_gpu_init()
3440 rdev->config.evergreen.tile_config |= 2 << 4; in evergreen_gpu_init()
3444 rdev->config.evergreen.tile_config |= 0 << 8; in evergreen_gpu_init()
3445 rdev->config.evergreen.tile_config |= in evergreen_gpu_init()
3448 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) { in evergreen_gpu_init()
3458 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) { in evergreen_gpu_init()
3471 for (i = 0; i < rdev->config.evergreen.max_backends; i++) in evergreen_gpu_init()
3475 for (i = 0; i < rdev->config.evergreen.max_backends; i++) in evergreen_gpu_init()
3479 for (i = 0; i < rdev->config.evergreen.num_ses; i++) { in evergreen_gpu_init()
3485 simd_disable_bitmap |= 0xffffffff << rdev->config.evergreen.max_simds; in evergreen_gpu_init()
3489 rdev->config.evergreen.active_simds = hweight32(~tmp); in evergreen_gpu_init()
3502 if ((rdev->config.evergreen.max_backends == 1) && in evergreen_gpu_init()
3503 (rdev->flags & RADEON_IS_IGP)) { in evergreen_gpu_init()
3513 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends, in evergreen_gpu_init()
3516 rdev->config.evergreen.backend_map = tmp; in evergreen_gpu_init()
3542 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets); in evergreen_gpu_init()
3545 if (rdev->family <= CHIP_SUMO2) in evergreen_gpu_init()
3548 …WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) … in evergreen_gpu_init()
3549 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) | in evergreen_gpu_init()
3550 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1))); in evergreen_gpu_init()
3552 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) | in evergreen_gpu_init()
3553 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) | in evergreen_gpu_init()
3554 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size))); in evergreen_gpu_init()
3561 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) | in evergreen_gpu_init()
3578 switch (rdev->family) { in evergreen_gpu_init()
3593 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32); in evergreen_gpu_init()
3594 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32); in evergreen_gpu_init()
3596 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); in evergreen_gpu_init()
3597 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32); in evergreen_gpu_init()
3598 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); in evergreen_gpu_init()
3599 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); in evergreen_gpu_init()
3601 switch (rdev->family) { in evergreen_gpu_init()
3614 …sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)… in evergreen_gpu_init()
3615 …sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)… in evergreen_gpu_init()
3616 …sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count)… in evergreen_gpu_init()
3617 …sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count… in evergreen_gpu_init()
3618 …sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_coun… in evergreen_gpu_init()
3620 …sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6… in evergreen_gpu_init()
3621 …sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / … in evergreen_gpu_init()
3622 …sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6… in evergreen_gpu_init()
3623 …sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / … in evergreen_gpu_init()
3624 …sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6… in evergreen_gpu_init()
3625 …sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / … in evergreen_gpu_init()
3642 switch (rdev->family) { in evergreen_gpu_init()
3706 int evergreen_mc_init(struct radeon_device *rdev) in evergreen_mc_init() argument
3712 rdev->mc.vram_is_ddr = true; in evergreen_mc_init()
3713 if ((rdev->family == CHIP_PALM) || in evergreen_mc_init()
3714 (rdev->family == CHIP_SUMO) || in evergreen_mc_init()
3715 (rdev->family == CHIP_SUMO2)) in evergreen_mc_init()
3742 rdev->mc.vram_width = numchan * chansize; in evergreen_mc_init()
3744 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in evergreen_mc_init()
3745 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in evergreen_mc_init()
3747 if ((rdev->family == CHIP_PALM) || in evergreen_mc_init()
3748 (rdev->family == CHIP_SUMO) || in evergreen_mc_init()
3749 (rdev->family == CHIP_SUMO2)) { in evergreen_mc_init()
3751 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); in evergreen_mc_init()
3752 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); in evergreen_mc_init()
3755 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in evergreen_mc_init()
3756 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL; in evergreen_mc_init()
3758 rdev->mc.visible_vram_size = rdev->mc.aper_size; in evergreen_mc_init()
3759 r700_vram_gtt_location(rdev, &rdev->mc); in evergreen_mc_init()
3760 radeon_update_bandwidth_info(rdev); in evergreen_mc_init()
3765 void evergreen_print_gpu_status_regs(struct radeon_device *rdev) in evergreen_print_gpu_status_regs() argument
3767 dev_info(rdev->dev, " GRBM_STATUS = 0x%08X\n", in evergreen_print_gpu_status_regs()
3769 dev_info(rdev->dev, " GRBM_STATUS_SE0 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3771 dev_info(rdev->dev, " GRBM_STATUS_SE1 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3773 dev_info(rdev->dev, " SRBM_STATUS = 0x%08X\n", in evergreen_print_gpu_status_regs()
3775 dev_info(rdev->dev, " SRBM_STATUS2 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3777 dev_info(rdev->dev, " R_008674_CP_STALLED_STAT1 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3779 dev_info(rdev->dev, " R_008678_CP_STALLED_STAT2 = 0x%08X\n", in evergreen_print_gpu_status_regs()
3781 dev_info(rdev->dev, " R_00867C_CP_BUSY_STAT = 0x%08X\n", in evergreen_print_gpu_status_regs()
3783 dev_info(rdev->dev, " R_008680_CP_STAT = 0x%08X\n", in evergreen_print_gpu_status_regs()
3785 dev_info(rdev->dev, " R_00D034_DMA_STATUS_REG = 0x%08X\n", in evergreen_print_gpu_status_regs()
3787 if (rdev->family >= CHIP_CAYMAN) { in evergreen_print_gpu_status_regs()
3788 dev_info(rdev->dev, " R_00D834_DMA_STATUS_REG = 0x%08X\n", in evergreen_print_gpu_status_regs()
3793 bool evergreen_is_display_hung(struct radeon_device *rdev) in evergreen_is_display_hung() argument
3799 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_is_display_hung()
3807 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_is_display_hung()
3822 u32 evergreen_gpu_check_soft_reset(struct radeon_device *rdev) in evergreen_gpu_check_soft_reset() argument
3874 if (evergreen_is_display_hung(rdev)) in evergreen_gpu_check_soft_reset()
3891 static void evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask) in evergreen_gpu_soft_reset() argument
3900 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask); in evergreen_gpu_soft_reset()
3902 evergreen_print_gpu_status_regs(rdev); in evergreen_gpu_soft_reset()
3916 evergreen_mc_stop(rdev, &save); in evergreen_gpu_soft_reset()
3917 if (evergreen_mc_wait_for_idle(rdev)) { in evergreen_gpu_soft_reset()
3918 dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); in evergreen_gpu_soft_reset()
3963 if (!(rdev->flags & RADEON_IS_IGP)) { in evergreen_gpu_soft_reset()
3971 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); in evergreen_gpu_soft_reset()
3985 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); in evergreen_gpu_soft_reset()
3999 evergreen_mc_resume(rdev, &save); in evergreen_gpu_soft_reset()
4002 evergreen_print_gpu_status_regs(rdev); in evergreen_gpu_soft_reset()
4005 void evergreen_gpu_pci_config_reset(struct radeon_device *rdev) in evergreen_gpu_pci_config_reset() argument
4010 dev_info(rdev->dev, "GPU pci config reset\n"); in evergreen_gpu_pci_config_reset()
4024 r600_rlc_stop(rdev); in evergreen_gpu_pci_config_reset()
4029 rv770_set_clk_bypass_mode(rdev); in evergreen_gpu_pci_config_reset()
4031 pci_clear_master(rdev->pdev); in evergreen_gpu_pci_config_reset()
4033 evergreen_mc_stop(rdev, &save); in evergreen_gpu_pci_config_reset()
4034 if (evergreen_mc_wait_for_idle(rdev)) { in evergreen_gpu_pci_config_reset()
4035 dev_warn(rdev->dev, "Wait for MC idle timed out !\n"); in evergreen_gpu_pci_config_reset()
4038 radeon_pci_config_reset(rdev); in evergreen_gpu_pci_config_reset()
4040 for (i = 0; i < rdev->usec_timeout; i++) { in evergreen_gpu_pci_config_reset()
4047 int evergreen_asic_reset(struct radeon_device *rdev, bool hard) in evergreen_asic_reset() argument
4052 evergreen_gpu_pci_config_reset(rdev); in evergreen_asic_reset()
4056 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_asic_reset()
4059 r600_set_bios_scratch_engine_hung(rdev, true); in evergreen_asic_reset()
4062 evergreen_gpu_soft_reset(rdev, reset_mask); in evergreen_asic_reset()
4064 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_asic_reset()
4068 evergreen_gpu_pci_config_reset(rdev); in evergreen_asic_reset()
4070 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_asic_reset()
4073 r600_set_bios_scratch_engine_hung(rdev, false); in evergreen_asic_reset()
4087 bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) in evergreen_gfx_is_lockup() argument
4089 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev); in evergreen_gfx_is_lockup()
4094 radeon_ring_lockup_update(rdev, ring); in evergreen_gfx_is_lockup()
4097 return radeon_ring_test_lockup(rdev, ring); in evergreen_gfx_is_lockup()
4106 void sumo_rlc_fini(struct radeon_device *rdev) in sumo_rlc_fini() argument
4111 if (rdev->rlc.save_restore_obj) { in sumo_rlc_fini()
4112 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_fini()
4114 dev_warn(rdev->dev, "(%d) reserve RLC sr bo failed\n", r); in sumo_rlc_fini()
4115 radeon_bo_unpin(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4116 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4118 radeon_bo_unref(&rdev->rlc.save_restore_obj); in sumo_rlc_fini()
4119 rdev->rlc.save_restore_obj = NULL; in sumo_rlc_fini()
4123 if (rdev->rlc.clear_state_obj) { in sumo_rlc_fini()
4124 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_fini()
4126 dev_warn(rdev->dev, "(%d) reserve RLC c bo failed\n", r); in sumo_rlc_fini()
4127 radeon_bo_unpin(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4128 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4130 radeon_bo_unref(&rdev->rlc.clear_state_obj); in sumo_rlc_fini()
4131 rdev->rlc.clear_state_obj = NULL; in sumo_rlc_fini()
4135 if (rdev->rlc.cp_table_obj) { in sumo_rlc_fini()
4136 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false); in sumo_rlc_fini()
4138 dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r); in sumo_rlc_fini()
4139 radeon_bo_unpin(rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4140 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4142 radeon_bo_unref(&rdev->rlc.cp_table_obj); in sumo_rlc_fini()
4143 rdev->rlc.cp_table_obj = NULL; in sumo_rlc_fini()
4149 int sumo_rlc_init(struct radeon_device *rdev) in sumo_rlc_init() argument
4159 src_ptr = rdev->rlc.reg_list; in sumo_rlc_init()
4160 dws = rdev->rlc.reg_list_size; in sumo_rlc_init()
4161 if (rdev->family >= CHIP_BONAIRE) { in sumo_rlc_init()
4164 cs_data = rdev->rlc.cs_data; in sumo_rlc_init()
4168 if (rdev->rlc.save_restore_obj == NULL) { in sumo_rlc_init()
4169 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true, in sumo_rlc_init()
4171 NULL, &rdev->rlc.save_restore_obj); in sumo_rlc_init()
4173 dev_warn(rdev->dev, "(%d) create RLC sr bo failed\n", r); in sumo_rlc_init()
4178 r = radeon_bo_reserve(rdev->rlc.save_restore_obj, false); in sumo_rlc_init()
4180 sumo_rlc_fini(rdev); in sumo_rlc_init()
4183 r = radeon_bo_pin(rdev->rlc.save_restore_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4184 &rdev->rlc.save_restore_gpu_addr); in sumo_rlc_init()
4186 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4187 dev_warn(rdev->dev, "(%d) pin RLC sr bo failed\n", r); in sumo_rlc_init()
4188 sumo_rlc_fini(rdev); in sumo_rlc_init()
4192 r = radeon_bo_kmap(rdev->rlc.save_restore_obj, (void **)&rdev->rlc.sr_ptr); in sumo_rlc_init()
4194 dev_warn(rdev->dev, "(%d) map RLC sr bo failed\n", r); in sumo_rlc_init()
4195 sumo_rlc_fini(rdev); in sumo_rlc_init()
4199 dst_ptr = rdev->rlc.sr_ptr; in sumo_rlc_init()
4200 if (rdev->family >= CHIP_TAHITI) { in sumo_rlc_init()
4202 for (i = 0; i < rdev->rlc.reg_list_size; i++) in sumo_rlc_init()
4222 radeon_bo_kunmap(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4223 radeon_bo_unreserve(rdev->rlc.save_restore_obj); in sumo_rlc_init()
4228 if (rdev->family >= CHIP_BONAIRE) { in sumo_rlc_init()
4229 rdev->rlc.clear_state_size = dws = cik_get_csb_size(rdev); in sumo_rlc_init()
4230 } else if (rdev->family >= CHIP_TAHITI) { in sumo_rlc_init()
4231 rdev->rlc.clear_state_size = si_get_csb_size(rdev); in sumo_rlc_init()
4232 dws = rdev->rlc.clear_state_size + (256 / 4); in sumo_rlc_init()
4244 rdev->rlc.clear_state_size = dws; in sumo_rlc_init()
4247 if (rdev->rlc.clear_state_obj == NULL) { in sumo_rlc_init()
4248 r = radeon_bo_create(rdev, dws * 4, PAGE_SIZE, true, in sumo_rlc_init()
4250 NULL, &rdev->rlc.clear_state_obj); in sumo_rlc_init()
4252 dev_warn(rdev->dev, "(%d) create RLC c bo failed\n", r); in sumo_rlc_init()
4253 sumo_rlc_fini(rdev); in sumo_rlc_init()
4257 r = radeon_bo_reserve(rdev->rlc.clear_state_obj, false); in sumo_rlc_init()
4259 sumo_rlc_fini(rdev); in sumo_rlc_init()
4262 r = radeon_bo_pin(rdev->rlc.clear_state_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4263 &rdev->rlc.clear_state_gpu_addr); in sumo_rlc_init()
4265 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4266 dev_warn(rdev->dev, "(%d) pin RLC c bo failed\n", r); in sumo_rlc_init()
4267 sumo_rlc_fini(rdev); in sumo_rlc_init()
4271 r = radeon_bo_kmap(rdev->rlc.clear_state_obj, (void **)&rdev->rlc.cs_ptr); in sumo_rlc_init()
4273 dev_warn(rdev->dev, "(%d) map RLC c bo failed\n", r); in sumo_rlc_init()
4274 sumo_rlc_fini(rdev); in sumo_rlc_init()
4278 dst_ptr = rdev->rlc.cs_ptr; in sumo_rlc_init()
4279 if (rdev->family >= CHIP_BONAIRE) { in sumo_rlc_init()
4280 cik_get_csb_buffer(rdev, dst_ptr); in sumo_rlc_init()
4281 } else if (rdev->family >= CHIP_TAHITI) { in sumo_rlc_init()
4282 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + 256; in sumo_rlc_init()
4285 dst_ptr[2] = cpu_to_le32(rdev->rlc.clear_state_size); in sumo_rlc_init()
4286 si_get_csb_buffer(rdev, &dst_ptr[(256/4)]); in sumo_rlc_init()
4289 reg_list_mc_addr = rdev->rlc.clear_state_gpu_addr + (reg_list_blk_index * 4); in sumo_rlc_init()
4318 radeon_bo_kunmap(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4319 radeon_bo_unreserve(rdev->rlc.clear_state_obj); in sumo_rlc_init()
4322 if (rdev->rlc.cp_table_size) { in sumo_rlc_init()
4323 if (rdev->rlc.cp_table_obj == NULL) { in sumo_rlc_init()
4324 r = radeon_bo_create(rdev, rdev->rlc.cp_table_size, in sumo_rlc_init()
4327 NULL, &rdev->rlc.cp_table_obj); in sumo_rlc_init()
4329 dev_warn(rdev->dev, "(%d) create RLC cp table bo failed\n", r); in sumo_rlc_init()
4330 sumo_rlc_fini(rdev); in sumo_rlc_init()
4335 r = radeon_bo_reserve(rdev->rlc.cp_table_obj, false); in sumo_rlc_init()
4337 dev_warn(rdev->dev, "(%d) reserve RLC cp table bo failed\n", r); in sumo_rlc_init()
4338 sumo_rlc_fini(rdev); in sumo_rlc_init()
4341 r = radeon_bo_pin(rdev->rlc.cp_table_obj, RADEON_GEM_DOMAIN_VRAM, in sumo_rlc_init()
4342 &rdev->rlc.cp_table_gpu_addr); in sumo_rlc_init()
4344 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4345 dev_warn(rdev->dev, "(%d) pin RLC cp_table bo failed\n", r); in sumo_rlc_init()
4346 sumo_rlc_fini(rdev); in sumo_rlc_init()
4349 r = radeon_bo_kmap(rdev->rlc.cp_table_obj, (void **)&rdev->rlc.cp_table_ptr); in sumo_rlc_init()
4351 dev_warn(rdev->dev, "(%d) map RLC cp table bo failed\n", r); in sumo_rlc_init()
4352 sumo_rlc_fini(rdev); in sumo_rlc_init()
4356 cik_init_cp_pg_table(rdev); in sumo_rlc_init()
4358 radeon_bo_kunmap(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4359 radeon_bo_unreserve(rdev->rlc.cp_table_obj); in sumo_rlc_init()
4366 static void evergreen_rlc_start(struct radeon_device *rdev) in evergreen_rlc_start() argument
4370 if (rdev->flags & RADEON_IS_IGP) { in evergreen_rlc_start()
4377 int evergreen_rlc_resume(struct radeon_device *rdev) in evergreen_rlc_resume() argument
4382 if (!rdev->rlc_fw) in evergreen_rlc_resume()
4385 r600_rlc_stop(rdev); in evergreen_rlc_resume()
4389 if (rdev->flags & RADEON_IS_IGP) { in evergreen_rlc_resume()
4390 if (rdev->family == CHIP_ARUBA) { in evergreen_rlc_resume()
4392 3 | (3 << (16 * rdev->config.cayman.max_shader_engines)); in evergreen_rlc_resume()
4395 tmp |= 0xffffffff << rdev->config.cayman.max_simds_per_se; in evergreen_rlc_resume()
4397 if (tmp == rdev->config.cayman.max_simds_per_se) { in evergreen_rlc_resume()
4408 WREG32(TN_RLC_SAVE_AND_RESTORE_BASE, rdev->rlc.save_restore_gpu_addr >> 8); in evergreen_rlc_resume()
4409 WREG32(TN_RLC_CLEAR_STATE_RESTORE_BASE, rdev->rlc.clear_state_gpu_addr >> 8); in evergreen_rlc_resume()
4420 fw_data = (const __be32 *)rdev->rlc_fw->data; in evergreen_rlc_resume()
4421 if (rdev->family >= CHIP_ARUBA) { in evergreen_rlc_resume()
4426 } else if (rdev->family >= CHIP_CAYMAN) { in evergreen_rlc_resume()
4439 evergreen_rlc_start(rdev); in evergreen_rlc_resume()
4446 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc) in evergreen_get_vblank_counter() argument
4448 if (crtc >= rdev->num_crtc) in evergreen_get_vblank_counter()
4454 void evergreen_disable_interrupt_state(struct radeon_device *rdev) in evergreen_disable_interrupt_state() argument
4459 if (rdev->family >= CHIP_CAYMAN) { in evergreen_disable_interrupt_state()
4460 cayman_cp_int_cntl_setup(rdev, 0, in evergreen_disable_interrupt_state()
4462 cayman_cp_int_cntl_setup(rdev, 1, 0); in evergreen_disable_interrupt_state()
4463 cayman_cp_int_cntl_setup(rdev, 2, 0); in evergreen_disable_interrupt_state()
4472 for (i = 0; i < rdev->num_crtc; i++) in evergreen_disable_interrupt_state()
4474 for (i = 0; i < rdev->num_crtc; i++) in evergreen_disable_interrupt_state()
4478 if (!ASIC_IS_DCE5(rdev)) in evergreen_disable_interrupt_state()
4487 int evergreen_irq_set(struct radeon_device *rdev) in evergreen_irq_set() argument
4496 if (!rdev->irq.installed) { in evergreen_irq_set()
4501 if (!rdev->ih.enabled) { in evergreen_irq_set()
4502 r600_disable_interrupts(rdev); in evergreen_irq_set()
4504 evergreen_disable_interrupt_state(rdev); in evergreen_irq_set()
4508 if (rdev->family == CHIP_ARUBA) in evergreen_irq_set()
4517 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_set()
4519 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in evergreen_irq_set()
4523 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) { in evergreen_irq_set()
4527 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) { in evergreen_irq_set()
4532 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in evergreen_irq_set()
4539 if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) { in evergreen_irq_set()
4544 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_set()
4546 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) { in evergreen_irq_set()
4552 if (rdev->irq.dpm_thermal) { in evergreen_irq_set()
4557 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_set()
4558 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); in evergreen_irq_set()
4559 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1); in evergreen_irq_set()
4560 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2); in evergreen_irq_set()
4566 if (rdev->family >= CHIP_CAYMAN) in evergreen_irq_set()
4571 for (i = 0; i < rdev->num_crtc; i++) { in evergreen_irq_set()
4573 rdev, INT_MASK + crtc_offsets[i], in evergreen_irq_set()
4575 rdev->irq.crtc_vblank_int[i] || in evergreen_irq_set()
4576 atomic_read(&rdev->irq.pflip[i]), "vblank", i); in evergreen_irq_set()
4579 for (i = 0; i < rdev->num_crtc; i++) in evergreen_irq_set()
4584 rdev, DC_HPDx_INT_CONTROL(i), in evergreen_irq_set()
4586 rdev->irq.hpd[i], "HPD", i); in evergreen_irq_set()
4589 if (rdev->family == CHIP_ARUBA) in evergreen_irq_set()
4596 rdev, AFMT_AUDIO_PACKET_CONTROL + crtc_offsets[i], in evergreen_irq_set()
4598 rdev->irq.afmt[i], "HDMI", i); in evergreen_irq_set()
4608 static void evergreen_irq_ack(struct radeon_device *rdev) in evergreen_irq_ack() argument
4611 u32 *grph_int = rdev->irq.stat_regs.evergreen.grph_int; in evergreen_irq_ack()
4612 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in evergreen_irq_ack()
4613 u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status; in evergreen_irq_ack()
4618 if (i < rdev->num_crtc) in evergreen_irq_ack()
4623 for (i = 0; i < rdev->num_crtc; i += 2) { in evergreen_irq_ack()
4657 static void evergreen_irq_disable(struct radeon_device *rdev) in evergreen_irq_disable() argument
4659 r600_disable_interrupts(rdev); in evergreen_irq_disable()
4662 evergreen_irq_ack(rdev); in evergreen_irq_disable()
4663 evergreen_disable_interrupt_state(rdev); in evergreen_irq_disable()
4666 void evergreen_irq_suspend(struct radeon_device *rdev) in evergreen_irq_suspend() argument
4668 evergreen_irq_disable(rdev); in evergreen_irq_suspend()
4669 r600_rlc_stop(rdev); in evergreen_irq_suspend()
4672 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev) in evergreen_get_ih_wptr() argument
4676 if (rdev->wb.enabled) in evergreen_get_ih_wptr()
4677 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); in evergreen_get_ih_wptr()
4687 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n", in evergreen_get_ih_wptr()
4688 wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); in evergreen_get_ih_wptr()
4689 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; in evergreen_get_ih_wptr()
4694 return (wptr & rdev->ih.ptr_mask); in evergreen_get_ih_wptr()
4697 int evergreen_irq_process(struct radeon_device *rdev) in evergreen_irq_process() argument
4699 u32 *disp_int = rdev->irq.stat_regs.evergreen.disp_int; in evergreen_irq_process()
4700 u32 *afmt_status = rdev->irq.stat_regs.evergreen.afmt_status; in evergreen_irq_process()
4714 if (!rdev->ih.enabled || rdev->shutdown) in evergreen_irq_process()
4717 wptr = evergreen_get_ih_wptr(rdev); in evergreen_irq_process()
4721 if (atomic_xchg(&rdev->ih.lock, 1)) in evergreen_irq_process()
4724 rptr = rdev->ih.rptr; in evergreen_irq_process()
4731 evergreen_irq_ack(rdev); in evergreen_irq_process()
4736 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff; in evergreen_irq_process()
4737 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff; in evergreen_irq_process()
4752 if (rdev->irq.crtc_vblank_int[crtc_idx]) { in evergreen_irq_process()
4753 drm_handle_vblank(rdev->ddev, crtc_idx); in evergreen_irq_process()
4754 rdev->pm.vblank_sync = true; in evergreen_irq_process()
4755 wake_up(&rdev->irq.vblank_queue); in evergreen_irq_process()
4757 if (atomic_read(&rdev->irq.pflip[crtc_idx])) { in evergreen_irq_process()
4758 radeon_crtc_handle_vblank(rdev, in evergreen_irq_process()
4788 radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); in evergreen_irq_process()
4836 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); in evergreen_irq_process()
4846 dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data); in evergreen_irq_process()
4847 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", in evergreen_irq_process()
4849 dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", in evergreen_irq_process()
4851 cayman_vm_decode_fault(rdev, status, addr); in evergreen_irq_process()
4857 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_irq_process()
4861 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_process()
4864 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_irq_process()
4867 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX); in evergreen_irq_process()
4870 radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX); in evergreen_irq_process()
4874 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_irq_process()
4878 radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX); in evergreen_irq_process()
4882 rdev->pm.dpm.thermal.high_to_low = false; in evergreen_irq_process()
4887 rdev->pm.dpm.thermal.high_to_low = true; in evergreen_irq_process()
4894 if (rdev->family >= CHIP_CAYMAN) { in evergreen_irq_process()
4896 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX); in evergreen_irq_process()
4906 rptr &= rdev->ih.ptr_mask; in evergreen_irq_process()
4910 schedule_work(&rdev->dp_work); in evergreen_irq_process()
4912 schedule_delayed_work(&rdev->hotplug_work, 0); in evergreen_irq_process()
4914 schedule_work(&rdev->audio_work); in evergreen_irq_process()
4915 if (queue_thermal && rdev->pm.dpm_enabled) in evergreen_irq_process()
4916 schedule_work(&rdev->pm.dpm.thermal.work); in evergreen_irq_process()
4917 rdev->ih.rptr = rptr; in evergreen_irq_process()
4918 atomic_set(&rdev->ih.lock, 0); in evergreen_irq_process()
4921 wptr = evergreen_get_ih_wptr(rdev); in evergreen_irq_process()
4928 static void evergreen_uvd_init(struct radeon_device *rdev) in evergreen_uvd_init() argument
4932 if (!rdev->has_uvd) in evergreen_uvd_init()
4935 r = radeon_uvd_init(rdev); in evergreen_uvd_init()
4937 dev_err(rdev->dev, "failed UVD (%d) init.\n", r); in evergreen_uvd_init()
4944 rdev->has_uvd = 0; in evergreen_uvd_init()
4947 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL; in evergreen_uvd_init()
4948 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096); in evergreen_uvd_init()
4951 static void evergreen_uvd_start(struct radeon_device *rdev) in evergreen_uvd_start() argument
4955 if (!rdev->has_uvd) in evergreen_uvd_start()
4958 r = uvd_v2_2_resume(rdev); in evergreen_uvd_start()
4960 dev_err(rdev->dev, "failed UVD resume (%d).\n", r); in evergreen_uvd_start()
4963 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX); in evergreen_uvd_start()
4965 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r); in evergreen_uvd_start()
4971 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0; in evergreen_uvd_start()
4974 static void evergreen_uvd_resume(struct radeon_device *rdev) in evergreen_uvd_resume() argument
4979 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size) in evergreen_uvd_resume()
4982 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX]; in evergreen_uvd_resume()
4983 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0)); in evergreen_uvd_resume()
4985 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r); in evergreen_uvd_resume()
4988 r = uvd_v1_0_init(rdev); in evergreen_uvd_resume()
4990 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r); in evergreen_uvd_resume()
4995 static int evergreen_startup(struct radeon_device *rdev) in evergreen_startup() argument
5001 evergreen_pcie_gen2_enable(rdev); in evergreen_startup()
5003 evergreen_program_aspm(rdev); in evergreen_startup()
5006 r = r600_vram_scratch_init(rdev); in evergreen_startup()
5010 evergreen_mc_program(rdev); in evergreen_startup()
5012 if (ASIC_IS_DCE5(rdev) && !rdev->pm.dpm_enabled) { in evergreen_startup()
5013 r = ni_mc_load_microcode(rdev); in evergreen_startup()
5020 if (rdev->flags & RADEON_IS_AGP) { in evergreen_startup()
5021 evergreen_agp_enable(rdev); in evergreen_startup()
5023 r = evergreen_pcie_gart_enable(rdev); in evergreen_startup()
5027 evergreen_gpu_init(rdev); in evergreen_startup()
5030 if (rdev->flags & RADEON_IS_IGP) { in evergreen_startup()
5031 rdev->rlc.reg_list = sumo_rlc_save_restore_register_list; in evergreen_startup()
5032 rdev->rlc.reg_list_size = in evergreen_startup()
5034 rdev->rlc.cs_data = evergreen_cs_data; in evergreen_startup()
5035 r = sumo_rlc_init(rdev); in evergreen_startup()
5043 r = radeon_wb_init(rdev); in evergreen_startup()
5047 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in evergreen_startup()
5049 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in evergreen_startup()
5053 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX); in evergreen_startup()
5055 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r); in evergreen_startup()
5059 evergreen_uvd_start(rdev); in evergreen_startup()
5062 if (!rdev->irq.installed) { in evergreen_startup()
5063 r = radeon_irq_kms_init(rdev); in evergreen_startup()
5068 r = r600_irq_init(rdev); in evergreen_startup()
5071 radeon_irq_kms_fini(rdev); in evergreen_startup()
5074 evergreen_irq_set(rdev); in evergreen_startup()
5076 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in evergreen_startup()
5077 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, in evergreen_startup()
5082 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; in evergreen_startup()
5083 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, in evergreen_startup()
5088 r = evergreen_cp_load_microcode(rdev); in evergreen_startup()
5091 r = evergreen_cp_resume(rdev); in evergreen_startup()
5094 r = r600_dma_resume(rdev); in evergreen_startup()
5098 evergreen_uvd_resume(rdev); in evergreen_startup()
5100 r = radeon_ib_pool_init(rdev); in evergreen_startup()
5102 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in evergreen_startup()
5106 r = radeon_audio_init(rdev); in evergreen_startup()
5115 int evergreen_resume(struct radeon_device *rdev) in evergreen_resume() argument
5122 if (radeon_asic_reset(rdev)) in evergreen_resume()
5123 dev_warn(rdev->dev, "GPU reset failed !\n"); in evergreen_resume()
5129 atom_asic_init(rdev->mode_info.atom_context); in evergreen_resume()
5132 evergreen_init_golden_registers(rdev); in evergreen_resume()
5134 if (rdev->pm.pm_method == PM_METHOD_DPM) in evergreen_resume()
5135 radeon_pm_resume(rdev); in evergreen_resume()
5137 rdev->accel_working = true; in evergreen_resume()
5138 r = evergreen_startup(rdev); in evergreen_resume()
5141 rdev->accel_working = false; in evergreen_resume()
5149 int evergreen_suspend(struct radeon_device *rdev) in evergreen_suspend() argument
5151 radeon_pm_suspend(rdev); in evergreen_suspend()
5152 radeon_audio_fini(rdev); in evergreen_suspend()
5153 if (rdev->has_uvd) { in evergreen_suspend()
5154 uvd_v1_0_fini(rdev); in evergreen_suspend()
5155 radeon_uvd_suspend(rdev); in evergreen_suspend()
5157 r700_cp_stop(rdev); in evergreen_suspend()
5158 r600_dma_stop(rdev); in evergreen_suspend()
5159 evergreen_irq_suspend(rdev); in evergreen_suspend()
5160 radeon_wb_disable(rdev); in evergreen_suspend()
5161 evergreen_pcie_gart_disable(rdev); in evergreen_suspend()
5172 int evergreen_init(struct radeon_device *rdev) in evergreen_init() argument
5177 if (!radeon_get_bios(rdev)) { in evergreen_init()
5178 if (ASIC_IS_AVIVO(rdev)) in evergreen_init()
5182 if (!rdev->is_atom_bios) { in evergreen_init()
5183 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n"); in evergreen_init()
5186 r = radeon_atombios_init(rdev); in evergreen_init()
5192 if (radeon_asic_reset(rdev)) in evergreen_init()
5193 dev_warn(rdev->dev, "GPU reset failed !\n"); in evergreen_init()
5195 if (!radeon_card_posted(rdev)) { in evergreen_init()
5196 if (!rdev->bios) { in evergreen_init()
5197 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); in evergreen_init()
5201 atom_asic_init(rdev->mode_info.atom_context); in evergreen_init()
5204 evergreen_init_golden_registers(rdev); in evergreen_init()
5206 r600_scratch_init(rdev); in evergreen_init()
5208 radeon_surface_init(rdev); in evergreen_init()
5210 radeon_get_clock_info(rdev->ddev); in evergreen_init()
5212 r = radeon_fence_driver_init(rdev); in evergreen_init()
5216 if (rdev->flags & RADEON_IS_AGP) { in evergreen_init()
5217 r = radeon_agp_init(rdev); in evergreen_init()
5219 radeon_agp_disable(rdev); in evergreen_init()
5222 r = evergreen_mc_init(rdev); in evergreen_init()
5226 r = radeon_bo_init(rdev); in evergreen_init()
5230 if (ASIC_IS_DCE5(rdev)) { in evergreen_init()
5231 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) { in evergreen_init()
5232 r = ni_init_microcode(rdev); in evergreen_init()
5239 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { in evergreen_init()
5240 r = r600_init_microcode(rdev); in evergreen_init()
5249 radeon_pm_init(rdev); in evergreen_init()
5251 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL; in evergreen_init()
5252 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024); in evergreen_init()
5254 rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL; in evergreen_init()
5255 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024); in evergreen_init()
5257 evergreen_uvd_init(rdev); in evergreen_init()
5259 rdev->ih.ring_obj = NULL; in evergreen_init()
5260 r600_ih_ring_init(rdev, 64 * 1024); in evergreen_init()
5262 r = r600_pcie_gart_init(rdev); in evergreen_init()
5266 rdev->accel_working = true; in evergreen_init()
5267 r = evergreen_startup(rdev); in evergreen_init()
5269 dev_err(rdev->dev, "disabling GPU acceleration\n"); in evergreen_init()
5270 r700_cp_fini(rdev); in evergreen_init()
5271 r600_dma_fini(rdev); in evergreen_init()
5272 r600_irq_fini(rdev); in evergreen_init()
5273 if (rdev->flags & RADEON_IS_IGP) in evergreen_init()
5274 sumo_rlc_fini(rdev); in evergreen_init()
5275 radeon_wb_fini(rdev); in evergreen_init()
5276 radeon_ib_pool_fini(rdev); in evergreen_init()
5277 radeon_irq_kms_fini(rdev); in evergreen_init()
5278 evergreen_pcie_gart_fini(rdev); in evergreen_init()
5279 rdev->accel_working = false; in evergreen_init()
5286 if (ASIC_IS_DCE5(rdev)) { in evergreen_init()
5287 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) { in evergreen_init()
5296 void evergreen_fini(struct radeon_device *rdev) in evergreen_fini() argument
5298 radeon_pm_fini(rdev); in evergreen_fini()
5299 radeon_audio_fini(rdev); in evergreen_fini()
5300 r700_cp_fini(rdev); in evergreen_fini()
5301 r600_dma_fini(rdev); in evergreen_fini()
5302 r600_irq_fini(rdev); in evergreen_fini()
5303 if (rdev->flags & RADEON_IS_IGP) in evergreen_fini()
5304 sumo_rlc_fini(rdev); in evergreen_fini()
5305 radeon_wb_fini(rdev); in evergreen_fini()
5306 radeon_ib_pool_fini(rdev); in evergreen_fini()
5307 radeon_irq_kms_fini(rdev); in evergreen_fini()
5308 uvd_v1_0_fini(rdev); in evergreen_fini()
5309 radeon_uvd_fini(rdev); in evergreen_fini()
5310 evergreen_pcie_gart_fini(rdev); in evergreen_fini()
5311 r600_vram_scratch_fini(rdev); in evergreen_fini()
5312 radeon_gem_fini(rdev); in evergreen_fini()
5313 radeon_fence_driver_fini(rdev); in evergreen_fini()
5314 radeon_agp_fini(rdev); in evergreen_fini()
5315 radeon_bo_fini(rdev); in evergreen_fini()
5316 radeon_atombios_fini(rdev); in evergreen_fini()
5317 kfree(rdev->bios); in evergreen_fini()
5318 rdev->bios = NULL; in evergreen_fini()
5321 void evergreen_pcie_gen2_enable(struct radeon_device *rdev) in evergreen_pcie_gen2_enable() argument
5328 if (rdev->flags & RADEON_IS_IGP) in evergreen_pcie_gen2_enable()
5331 if (!(rdev->flags & RADEON_IS_PCIE)) in evergreen_pcie_gen2_enable()
5335 if (ASIC_IS_X2(rdev)) in evergreen_pcie_gen2_enable()
5338 if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) && in evergreen_pcie_gen2_enable()
5339 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT)) in evergreen_pcie_gen2_enable()
5384 void evergreen_program_aspm(struct radeon_device *rdev) in evergreen_program_aspm() argument
5399 if (!(rdev->flags & RADEON_IS_PCIE)) in evergreen_program_aspm()
5402 switch (rdev->family) { in evergreen_program_aspm()
5419 if (rdev->flags & RADEON_IS_IGP) in evergreen_program_aspm()
5441 if (rdev->family >= CHIP_BARTS) in evergreen_program_aspm()
5448 if (rdev->family >= CHIP_BARTS) in evergreen_program_aspm()
5478 if (rdev->family >= CHIP_BARTS) { in evergreen_program_aspm()
5510 if (rdev->family >= CHIP_BARTS) { in evergreen_program_aspm()
5527 if (rdev->family < CHIP_BARTS) in evergreen_program_aspm()