Lines Matching refs:radeon_ring_write
3474 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_test()
3475 radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2)); in cik_ring_test()
3476 radeon_ring_write(ring, 0xDEADBEEF); in cik_ring_test()
3530 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_hdp_flush_cp_ring_emit()
3531 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(1) | /* write, wait, write */ in cik_hdp_flush_cp_ring_emit()
3534 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ >> 2); in cik_hdp_flush_cp_ring_emit()
3535 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE >> 2); in cik_hdp_flush_cp_ring_emit()
3536 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3537 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
3538 radeon_ring_write(ring, 0x20); /* poll interval */ in cik_hdp_flush_cp_ring_emit()
3559 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3560 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_gfx_ring_emit()
3564 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_gfx_ring_emit()
3565 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | in cik_fence_gfx_ring_emit()
3567 radeon_ring_write(ring, fence->seq - 1); in cik_fence_gfx_ring_emit()
3568 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
3571 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); in cik_fence_gfx_ring_emit()
3572 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_gfx_ring_emit()
3576 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_gfx_ring_emit()
3577 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2)); in cik_fence_gfx_ring_emit()
3578 radeon_ring_write(ring, fence->seq); in cik_fence_gfx_ring_emit()
3579 radeon_ring_write(ring, 0); in cik_fence_gfx_ring_emit()
3598 radeon_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5)); in cik_fence_compute_ring_emit()
3599 radeon_ring_write(ring, (EOP_TCL1_ACTION_EN | in cik_fence_compute_ring_emit()
3603 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2)); in cik_fence_compute_ring_emit()
3604 radeon_ring_write(ring, addr & 0xfffffffc); in cik_fence_compute_ring_emit()
3605 radeon_ring_write(ring, upper_32_bits(addr)); in cik_fence_compute_ring_emit()
3606 radeon_ring_write(ring, fence->seq); in cik_fence_compute_ring_emit()
3607 radeon_ring_write(ring, 0); in cik_fence_compute_ring_emit()
3629 radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); in cik_semaphore_ring_emit()
3630 radeon_ring_write(ring, lower_32_bits(addr)); in cik_semaphore_ring_emit()
3631 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); in cik_semaphore_ring_emit()
3635 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_semaphore_ring_emit()
3636 radeon_ring_write(ring, 0x0); in cik_semaphore_ring_emit()
3690 radeon_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5)); in cik_copy_cpdma()
3691 radeon_ring_write(ring, control); in cik_copy_cpdma()
3692 radeon_ring_write(ring, lower_32_bits(src_offset)); in cik_copy_cpdma()
3693 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_cpdma()
3694 radeon_ring_write(ring, lower_32_bits(dst_offset)); in cik_copy_cpdma()
3695 radeon_ring_write(ring, upper_32_bits(dst_offset)); in cik_copy_cpdma()
3696 radeon_ring_write(ring, cur_size_in_bytes); in cik_copy_cpdma()
3737 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0)); in cik_ring_ib_execute()
3738 radeon_ring_write(ring, 0); in cik_ring_ib_execute()
3745 radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); in cik_ring_ib_execute()
3746 radeon_ring_write(ring, ((ring->rptr_save_reg - in cik_ring_ib_execute()
3748 radeon_ring_write(ring, next_rptr); in cik_ring_ib_execute()
3751 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_ring_ib_execute()
3752 radeon_ring_write(ring, WRITE_DATA_DST_SEL(1)); in cik_ring_ib_execute()
3753 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); in cik_ring_ib_execute()
3754 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in cik_ring_ib_execute()
3755 radeon_ring_write(ring, next_rptr); in cik_ring_ib_execute()
3763 radeon_ring_write(ring, header); in cik_ring_ib_execute()
3764 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFFC)); in cik_ring_ib_execute()
3765 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF); in cik_ring_ib_execute()
3766 radeon_ring_write(ring, control); in cik_ring_ib_execute()
4000 radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2)); in cik_cp_gfx_start()
4001 radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE)); in cik_cp_gfx_start()
4002 radeon_ring_write(ring, 0x8000); in cik_cp_gfx_start()
4003 radeon_ring_write(ring, 0x8000); in cik_cp_gfx_start()
4006 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_cp_gfx_start()
4007 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); in cik_cp_gfx_start()
4009 radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1)); in cik_cp_gfx_start()
4010 radeon_ring_write(ring, 0x80000000); in cik_cp_gfx_start()
4011 radeon_ring_write(ring, 0x80000000); in cik_cp_gfx_start()
4014 radeon_ring_write(ring, cik_default_state[i]); in cik_cp_gfx_start()
4016 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); in cik_cp_gfx_start()
4017 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE); in cik_cp_gfx_start()
4020 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0)); in cik_cp_gfx_start()
4021 radeon_ring_write(ring, 0); in cik_cp_gfx_start()
4023 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); in cik_cp_gfx_start()
4024 radeon_ring_write(ring, 0x00000316); in cik_cp_gfx_start()
4025 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ in cik_cp_gfx_start()
4026 radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */ in cik_cp_gfx_start()
5693 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
5694 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
5697 radeon_ring_write(ring, in cik_vm_flush()
5700 radeon_ring_write(ring, in cik_vm_flush()
5703 radeon_ring_write(ring, 0); in cik_vm_flush()
5704 radeon_ring_write(ring, pd_addr >> 12); in cik_vm_flush()
5707 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
5708 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
5710 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_vm_flush()
5711 radeon_ring_write(ring, 0); in cik_vm_flush()
5712 radeon_ring_write(ring, VMID(vm_id)); in cik_vm_flush()
5714 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6)); in cik_vm_flush()
5715 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
5717 radeon_ring_write(ring, SH_MEM_BASES >> 2); in cik_vm_flush()
5718 radeon_ring_write(ring, 0); in cik_vm_flush()
5720 radeon_ring_write(ring, 0); /* SH_MEM_BASES */ in cik_vm_flush()
5721 radeon_ring_write(ring, SH_MEM_CONFIG_GFX_DEFAULT); /* SH_MEM_CONFIG */ in cik_vm_flush()
5722 radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */ in cik_vm_flush()
5723 radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */ in cik_vm_flush()
5725 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
5726 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
5728 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); in cik_vm_flush()
5729 radeon_ring_write(ring, 0); in cik_vm_flush()
5730 radeon_ring_write(ring, VMID(0)); in cik_vm_flush()
5736 radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); in cik_vm_flush()
5737 radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) | in cik_vm_flush()
5739 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_vm_flush()
5740 radeon_ring_write(ring, 0); in cik_vm_flush()
5741 radeon_ring_write(ring, 1 << vm_id); in cik_vm_flush()
5744 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); in cik_vm_flush()
5745 radeon_ring_write(ring, (WAIT_REG_MEM_OPERATION(0) | /* wait */ in cik_vm_flush()
5748 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); in cik_vm_flush()
5749 radeon_ring_write(ring, 0); in cik_vm_flush()
5750 radeon_ring_write(ring, 0); /* ref */ in cik_vm_flush()
5751 radeon_ring_write(ring, 0); /* mask */ in cik_vm_flush()
5752 radeon_ring_write(ring, 0x20); /* poll interval */ in cik_vm_flush()
5757 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); in cik_vm_flush()
5758 radeon_ring_write(ring, 0x0); in cik_vm_flush()