201 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)  in ci_get_ps()  argument
203 	struct ci_ps *ps = rps->ps_priv;  in ci_get_ps()
794 					struct radeon_ps *rps)  in ci_apply_state_adjust_rules()  argument
796 	struct ci_ps *ps = ci_get_ps(rps);  in ci_apply_state_adjust_rules()
803 	if (rps->vce_active) {  in ci_apply_state_adjust_rules()
804 		rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;  in ci_apply_state_adjust_rules()
805 		rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;  in ci_apply_state_adjust_rules()
807 		rps->evclk = 0;  in ci_apply_state_adjust_rules()
808 		rps->ecclk = 0;  in ci_apply_state_adjust_rules()
817 	if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)  in ci_apply_state_adjust_rules()
846 	if (rps->vce_active) {  in ci_apply_state_adjust_rules()
5105 				 struct radeon_ps *rps)  in ci_update_current_ps()  argument
5107 	struct ci_ps *new_ps = ci_get_ps(rps);  in ci_update_current_ps()
5110 	pi->current_rps = *rps;  in ci_update_current_ps()
5116 				   struct radeon_ps *rps)  in ci_update_requested_ps()  argument
5118 	struct ci_ps *new_ps = ci_get_ps(rps);  in ci_update_requested_ps()
5121 	pi->requested_rps = *rps;  in ci_update_requested_ps()
5448 					  struct radeon_ps *rps,  in ci_parse_pplib_non_clock_info()  argument
5452 	rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);  in ci_parse_pplib_non_clock_info()
5453 	rps->class = le16_to_cpu(non_clock_info->usClassification);  in ci_parse_pplib_non_clock_info()
5454 	rps->class2 = le16_to_cpu(non_clock_info->usClassification2);  in ci_parse_pplib_non_clock_info()
5457 		rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);  in ci_parse_pplib_non_clock_info()
5458 		rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);  in ci_parse_pplib_non_clock_info()
5460 		rps->vclk = 0;  in ci_parse_pplib_non_clock_info()
5461 		rps->dclk = 0;  in ci_parse_pplib_non_clock_info()
5464 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)  in ci_parse_pplib_non_clock_info()
5465 		rdev->pm.dpm.boot_ps = rps;  in ci_parse_pplib_non_clock_info()
5466 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)  in ci_parse_pplib_non_clock_info()
5467 		rdev->pm.dpm.uvd_ps = rps;  in ci_parse_pplib_non_clock_info()
5471 				      struct radeon_ps *rps, int index,  in ci_parse_pplib_clock_info()  argument
5475 	struct ci_ps *ps = ci_get_ps(rps);  in ci_parse_pplib_clock_info()
5493 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {  in ci_parse_pplib_clock_info()
5497 	if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {  in ci_parse_pplib_clock_info()
5504 	if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {  in ci_parse_pplib_clock_info()
5511 	switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {  in ci_parse_pplib_clock_info()
5941 	struct radeon_ps *rps = &pi->current_rps;  in ci_dpm_debugfs_print_current_performance_level()  local
5946 	seq_printf(m, "vce    %sabled\n", rps->vce_active ? "en" : "dis");  in ci_dpm_debugfs_print_current_performance_level()
5952 			      struct radeon_ps *rps)  in ci_dpm_print_power_state()  argument
5954 	struct ci_ps *ps = ci_get_ps(rps);  in ci_dpm_print_power_state()
5958 	r600_dpm_print_class_info(rps->class, rps->class2);  in ci_dpm_print_power_state()
5959 	r600_dpm_print_cap_info(rps->caps);  in ci_dpm_print_power_state()
5960 	printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);  in ci_dpm_print_power_state()
5966 	r600_dpm_print_ps_status(rdev, rps);  in ci_dpm_print_power_state()