336 	tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;  in ci_populate_tdc_limit()
417 	struct radeon_cac_tdp_table *cac_tdp_table =  in ci_populate_bapm_vddc_base_leakage_sidd()  local
418 		rdev->pm.dpm.dyn_state.cac_tdp_table;  in ci_populate_bapm_vddc_base_leakage_sidd()
420 	hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;  in ci_populate_bapm_vddc_base_leakage_sidd()
421 	lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;  in ci_populate_bapm_vddc_base_leakage_sidd()
434 	struct radeon_cac_tdp_table *cac_tdp_table =  in ci_populate_bapm_parameters_in_dpm_table()  local
435 		rdev->pm.dpm.dyn_state.cac_tdp_table;  in ci_populate_bapm_parameters_in_dpm_table()
441 	dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;  in ci_populate_bapm_parameters_in_dpm_table()
442 	dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;  in ci_populate_bapm_parameters_in_dpm_table()
669 					struct radeon_cac_tdp_table *cac_tdp_table =  in ci_enable_power_containment()  local
670 						rdev->pm.dpm.dyn_state.cac_tdp_table;  in ci_enable_power_containment()
672 						(u32)(cac_tdp_table->maximum_power_delivery_limit * 256);  in ci_enable_power_containment()
743 	struct radeon_cac_tdp_table *cac_tdp_table =  in ci_power_control_set_level()  local
744 		rdev->pm.dpm.dyn_state.cac_tdp_table;  in ci_power_control_set_level()
754 			      (s32)cac_tdp_table->configurable_tdp) / 100;  in ci_power_control_set_level()
1633 	struct radeon_cac_tdp_table *cac_tdp_table =
1634 		rdev->pm.dpm.dyn_state.cac_tdp_table;
1638 		power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1640 		power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);