Lines Matching refs:crtc_offset

1381 	WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0);  in dce4_crtc_do_set_base()
1383 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1385 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1387 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1389 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1391 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); in dce4_crtc_do_set_base()
1392 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in dce4_crtc_do_set_base()
1399 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1406 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1407 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1408 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1409 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1410 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); in dce4_crtc_do_set_base()
1411 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); in dce4_crtc_do_set_base()
1414 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); in dce4_crtc_do_set_base()
1415 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in dce4_crtc_do_set_base()
1418 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1421 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1425 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1432 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in dce4_crtc_do_set_base()
1436 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0); in dce4_crtc_do_set_base()
1581 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1592 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1595 radeon_crtc->crtc_offset, (u32) fb_location); in avivo_crtc_do_set_base()
1596 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); in avivo_crtc_do_set_base()
1598 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap); in avivo_crtc_do_set_base()
1601 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1607 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1608 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1609 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1610 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); in avivo_crtc_do_set_base()
1611 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); in avivo_crtc_do_set_base()
1612 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); in avivo_crtc_do_set_base()
1615 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); in avivo_crtc_do_set_base()
1616 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); in avivo_crtc_do_set_base()
1618 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1622 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1626 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, in avivo_crtc_do_set_base()
1630 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3); in avivo_crtc_do_set_base()
2153 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0); in atombios_crtc_disable()
2155 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0); in atombios_crtc_disable()
2218 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2221 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2224 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2227 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2230 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2233 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; in radeon_atombios_init_crtc()
2238 radeon_crtc->crtc_offset = in radeon_atombios_init_crtc()
2241 radeon_crtc->crtc_offset = 0; in radeon_atombios_init_crtc()