132 		BUG();  in DISPC_DEFAULT_COLOR()
149 		BUG();  in DISPC_TRANS_COLOR()
160 		BUG();  in DISPC_TIMING_H()
167 		BUG();  in DISPC_TIMING_H()
178 		BUG();  in DISPC_TIMING_V()
185 		BUG();  in DISPC_TIMING_V()
196 		BUG();  in DISPC_POL_FREQ()
203 		BUG();  in DISPC_POL_FREQ()
214 		BUG();  in DISPC_DIVISORo()
221 		BUG();  in DISPC_DIVISORo()
239 		BUG();  in DISPC_SIZE_MGR()
250 		BUG();  in DISPC_DATA_CYCLE1()
257 		BUG();  in DISPC_DATA_CYCLE1()
268 		BUG();  in DISPC_DATA_CYCLE2()
275 		BUG();  in DISPC_DATA_CYCLE2()
286 		BUG();  in DISPC_DATA_CYCLE3()
293 		BUG();  in DISPC_DATA_CYCLE3()
304 		BUG();  in DISPC_CPR_COEF_R()
311 		BUG();  in DISPC_CPR_COEF_R()
322 		BUG();  in DISPC_CPR_COEF_G()
329 		BUG();  in DISPC_CPR_COEF_G()
340 		BUG();  in DISPC_CPR_COEF_B()
347 		BUG();  in DISPC_CPR_COEF_B()
367 		BUG();  in DISPC_OVL_BASE()
384 		BUG();  in DISPC_BA0_OFFSET()
400 		BUG();  in DISPC_BA1_OFFSET()
409 		BUG();  in DISPC_BA0_UV_OFFSET()
420 		BUG();  in DISPC_BA0_UV_OFFSET()
429 		BUG();  in DISPC_BA1_UV_OFFSET()
440 		BUG();  in DISPC_BA1_UV_OFFSET()
455 		BUG();  in DISPC_POS_OFFSET()
471 		BUG();  in DISPC_SIZE_OFFSET()
488 		BUG();  in DISPC_ATTR_OFFSET()
497 		BUG();  in DISPC_ATTR2_OFFSET()
508 		BUG();  in DISPC_ATTR2_OFFSET()
525 		BUG();  in DISPC_FIFO_THRESH_OFFSET()
542 		BUG();  in DISPC_FIFO_SIZE_STATUS_OFFSET()
559 		BUG();  in DISPC_ROW_INC_OFFSET()
576 		BUG();  in DISPC_PIX_INC_OFFSET()
589 		BUG();  in DISPC_WINDOW_SKIP_OFFSET()
592 		BUG();  in DISPC_WINDOW_SKIP_OFFSET()
605 		BUG();  in DISPC_TABLE_BA_OFFSET()
608 		BUG();  in DISPC_TABLE_BA_OFFSET()
617 		BUG();  in DISPC_FIR_OFFSET()
626 		BUG();  in DISPC_FIR_OFFSET()
635 		BUG();  in DISPC_FIR2_OFFSET()
646 		BUG();  in DISPC_FIR2_OFFSET()
655 		BUG();  in DISPC_PIC_SIZE_OFFSET()
664 		BUG();  in DISPC_PIC_SIZE_OFFSET()
674 		BUG();  in DISPC_ACCU0_OFFSET()
683 		BUG();  in DISPC_ACCU0_OFFSET()
692 		BUG();  in DISPC_ACCU2_0_OFFSET()
703 		BUG();  in DISPC_ACCU2_0_OFFSET()
712 		BUG();  in DISPC_ACCU1_OFFSET()
721 		BUG();  in DISPC_ACCU1_OFFSET()
730 		BUG();  in DISPC_ACCU2_1_OFFSET()
741 		BUG();  in DISPC_ACCU2_1_OFFSET()
751 		BUG();  in DISPC_FIR_COEF_H_OFFSET()
760 		BUG();  in DISPC_FIR_COEF_H_OFFSET()
770 		BUG();  in DISPC_FIR_COEF_H2_OFFSET()
781 		BUG();  in DISPC_FIR_COEF_H2_OFFSET()
791 		BUG();  in DISPC_FIR_COEF_HV_OFFSET()
800 		BUG();  in DISPC_FIR_COEF_HV_OFFSET()
810 		BUG();  in DISPC_FIR_COEF_HV2_OFFSET()
821 		BUG();  in DISPC_FIR_COEF_HV2_OFFSET()
831 		BUG();  in DISPC_CONV_COEF_OFFSET()
839 		BUG();  in DISPC_CONV_COEF_OFFSET()
849 		BUG();  in DISPC_FIR_COEF_V_OFFSET()
859 		BUG();  in DISPC_FIR_COEF_V_OFFSET()
869 		BUG();  in DISPC_FIR_COEF_V2_OFFSET()
880 		BUG();  in DISPC_FIR_COEF_V2_OFFSET()
897 		BUG();  in DISPC_PRELOAD_OFFSET()
916 		BUG();  in DISPC_MFLAG_THRESHOLD_OFFSET()