62 	FLD_GET(dispc_read_reg(dispc, idx), start, end)
66 			FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
374 static inline u32 dispc_read_reg(struct dispc_device *dispc, u16 idx)  in dispc_read_reg()  function
438 	dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg)
1190 	val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));  in dispc_ovl_set_channel_out()
1251 	val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));  in dispc_ovl_get_channel_out()
1362 	val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));  in dispc_ovl_set_vid_color_conv()
1428 		v = dispc_read_reg(dispc, DISPC_GLOBAL_BUFFER);  in dispc_init_fifos()
1862 	l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));  in dispc_ovl_set_scaling_common()
2858 	l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));  in dispc_wb_setup()
3062 	l = dispc_read_reg(dispc, DISPC_CONTROL);  in dispc_mgr_set_io_pad_mode()
3305 	l = dispc_read_reg(dispc, DISPC_DIVISORo(channel));  in dispc_mgr_get_lcd_divisor()
3371 		l = dispc_read_reg(dispc, DISPC_DIVISORo(channel));  in dispc_mgr_pclk_rate()
3460 		l = dispc_read_reg(dispc, DISPC_DIVISOR);  in dispc_dump_clocks()
3497 	seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r))  in dispc_dump_regs()
3532 	dispc_read_reg(dispc, DISPC_REG(i, r)))  in dispc_dump_regs()
3636 	dispc_read_reg(dispc, DISPC_REG(plane, name, i)))  in dispc_dump_regs()
3782 	return dispc_read_reg(dispc, DISPC_IRQSTATUS);  in dispc_read_irqstatus()
3792 	u32 old_mask = dispc_read_reg(dispc, DISPC_IRQENABLE);  in dispc_write_irqenable()
3800 	dispc_read_reg(dispc, DISPC_IRQENABLE);  in dispc_write_irqenable()
3954 		l = dispc_read_reg(dispc, DISPC_DIVISOR);  in _omap_dispc_initial_config()
4856 	rev = dispc_read_reg(dispc, DISPC_REVISION);  in dispc_bind()