44 	struct nv50_dmaobj *dmaobj = nv50_dmaobj(base);  in nv50_dmaobj_bind()  local
45 	struct nvkm_device *device = dmaobj->base.dma->engine.subdev.device;  in nv50_dmaobj_bind()
51 		nvkm_wo32(*pgpuobj, 0x00, dmaobj->flags0);  in nv50_dmaobj_bind()
52 		nvkm_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->base.limit));  in nv50_dmaobj_bind()
53 		nvkm_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->base.start));  in nv50_dmaobj_bind()
54 		nvkm_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->base.limit) << 24 |  in nv50_dmaobj_bind()
55 					  upper_32_bits(dmaobj->base.start));  in nv50_dmaobj_bind()
57 		nvkm_wo32(*pgpuobj, 0x14, dmaobj->flags5);  in nv50_dmaobj_bind()
77 	struct nv50_dmaobj *dmaobj;  in nv50_dmaobj_new()  local
81 	if (!(dmaobj = kzalloc(sizeof(*dmaobj), GFP_KERNEL)))  in nv50_dmaobj_new()
83 	*pdmaobj = &dmaobj->base;  in nv50_dmaobj_new()
86 			       &data, &size, &dmaobj->base);  in nv50_dmaobj_new()
105 		if (dmaobj->base.target != NV_MEM_TARGET_VM) {  in nv50_dmaobj_new()
121 	dmaobj->flags0 = (comp << 29) | (kind << 22) | (user << 20) |  in nv50_dmaobj_new()
123 	dmaobj->flags5 = (part << 16);  in nv50_dmaobj_new()
125 	switch (dmaobj->base.target) {  in nv50_dmaobj_new()
127 		dmaobj->flags0 |= 0x00000000;  in nv50_dmaobj_new()
130 		dmaobj->flags0 |= 0x00010000;  in nv50_dmaobj_new()
133 		dmaobj->flags0 |= 0x00020000;  in nv50_dmaobj_new()
136 		dmaobj->flags0 |= 0x00030000;  in nv50_dmaobj_new()
142 	switch (dmaobj->base.access) {  in nv50_dmaobj_new()
146 		dmaobj->flags0 |= 0x00040000;  in nv50_dmaobj_new()
150 		dmaobj->flags0 |= 0x00080000;  in nv50_dmaobj_new()