32 gv100_disp_wndw_cnt(struct nvkm_disp *disp, unsigned long *pmask)  in gv100_disp_wndw_cnt()  argument
34 	struct nvkm_device *device = disp->engine.subdev.device;  in gv100_disp_wndw_cnt()
42 	struct nv50_disp *disp =  in gv100_disp_super()  local
44 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_super()
50 	nvkm_debug(subdev, "supervisor %d: %08x\n", ffs(disp->super), stat);  in gv100_disp_super()
51 	list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
56 	if (disp->super & 0x00000001) {  in gv100_disp_super()
57 		nv50_disp_chan_mthd(disp->chan[0], NV_DBG_DEBUG);  in gv100_disp_super()
58 		nv50_disp_super_1(disp);  in gv100_disp_super()
59 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
62 			nv50_disp_super_1_0(disp, head);  in gv100_disp_super()
65 	if (disp->super & 0x00000002) {  in gv100_disp_super()
66 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
69 			nv50_disp_super_2_0(disp, head);  in gv100_disp_super()
71 		nvkm_outp_route(&disp->base);  in gv100_disp_super()
72 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
75 			nv50_disp_super_2_1(disp, head);  in gv100_disp_super()
77 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
80 			nv50_disp_super_2_2(disp, head);  in gv100_disp_super()
83 	if (disp->super & 0x00000004) {  in gv100_disp_super()
84 		list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_super()
87 			nv50_disp_super_3_0(disp, head);  in gv100_disp_super()
91 	list_for_each_entry(head, &disp->base.head, head)  in gv100_disp_super()
97 gv100_disp_exception(struct nv50_disp *disp, int chid)  in gv100_disp_exception()  argument
99 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_exception()
111 	if (chid < ARRAY_SIZE(disp->chan) && disp->chan[chid]) {  in gv100_disp_exception()
114 			nv50_disp_chan_mthd(disp->chan[chid], NV_DBG_ERROR);  in gv100_disp_exception()
125 gv100_disp_intr_ctrl_disp(struct nv50_disp *disp)  in gv100_disp_intr_ctrl_disp()  argument
127 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_intr_ctrl_disp()
132 		disp->super = (stat & 0x00000007);  in gv100_disp_intr_ctrl_disp()
133 		queue_work(disp->wq, &disp->supervisor);  in gv100_disp_intr_ctrl_disp()
134 		nvkm_wr32(device, 0x611860, disp->super);  in gv100_disp_intr_ctrl_disp()
154 			nv50_disp_chan_uevent_send(disp, 0);  in gv100_disp_intr_ctrl_disp()
157 		for_each_set_bit(wndw, &wndws, disp->wndw.nr) {  in gv100_disp_intr_ctrl_disp()
158 			nv50_disp_chan_uevent_send(disp, 1 + wndw);  in gv100_disp_intr_ctrl_disp()
167 gv100_disp_intr_exc_other(struct nv50_disp *disp)  in gv100_disp_intr_exc_other()  argument
169 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_intr_exc_other()
177 		gv100_disp_exception(disp, 0);  in gv100_disp_intr_exc_other()
182 		for_each_set_bit(head, &mask, disp->wndw.nr) {  in gv100_disp_intr_exc_other()
184 			gv100_disp_exception(disp, 73 + head);  in gv100_disp_intr_exc_other()
196 gv100_disp_intr_exc_winim(struct nv50_disp *disp)  in gv100_disp_intr_exc_winim()  argument
198 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_intr_exc_winim()
203 	for_each_set_bit(wndw, &stat, disp->wndw.nr) {  in gv100_disp_intr_exc_winim()
205 		gv100_disp_exception(disp, 33 + wndw);  in gv100_disp_intr_exc_winim()
216 gv100_disp_intr_exc_win(struct nv50_disp *disp)  in gv100_disp_intr_exc_win()  argument
218 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_intr_exc_win()
223 	for_each_set_bit(wndw, &stat, disp->wndw.nr) {  in gv100_disp_intr_exc_win()
225 		gv100_disp_exception(disp, 1 + wndw);  in gv100_disp_intr_exc_win()
236 gv100_disp_intr_head_timing(struct nv50_disp *disp, int head)  in gv100_disp_intr_head_timing()  argument
238 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_intr_head_timing()
249 		nvkm_disp_vblank(&disp->base, head);  in gv100_disp_intr_head_timing()
261 gv100_disp_intr(struct nv50_disp *disp)  in gv100_disp_intr()  argument
263 	struct nvkm_subdev *subdev = &disp->base.engine.subdev;  in gv100_disp_intr()
271 			gv100_disp_intr_head_timing(disp, head);  in gv100_disp_intr()
277 		gv100_disp_intr_exc_win(disp);  in gv100_disp_intr()
282 		gv100_disp_intr_exc_winim(disp);  in gv100_disp_intr()
287 		gv100_disp_intr_exc_other(disp);  in gv100_disp_intr()
292 		gv100_disp_intr_ctrl_disp(disp);  in gv100_disp_intr()
301 gv100_disp_fini(struct nv50_disp *disp)  in gv100_disp_fini()  argument
303 	struct nvkm_device *device = disp->base.engine.subdev.device;  in gv100_disp_fini()
308 gv100_disp_init(struct nv50_disp *disp)  in gv100_disp_init()  argument
310 	struct nvkm_device *device = disp->base.engine.subdev.device;  in gv100_disp_init()
330 	for (i = 0; i < disp->sor.nr; i++) {  in gv100_disp_init()
337 	list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_init()
352 	for (i = 0; i < disp->wndw.nr; i++) {  in gv100_disp_init()
369 	switch (nvkm_memory_target(disp->inst->memory)) {  in gv100_disp_init()
377 	nvkm_wr32(device, 0x610014, disp->inst->addr >> 16);  in gv100_disp_init()
384 	nvkm_wr32(device, 0x611cec, disp->head.mask << 16 |  in gv100_disp_init()
389 	nvkm_wr32(device, 0x611ce8, disp->wndw.mask); /* MSK. */  in gv100_disp_init()
393 	nvkm_wr32(device, 0x611ce4, disp->wndw.mask); /* MSK. */  in gv100_disp_init()
397 	list_for_each_entry(head, &disp->base.head, head) {  in gv100_disp_init()