368 	struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);  in nv50_dac_enable()  local
373 	core->func->dac->ctrl(core, nv_encoder->or, 1 << nv_crtc->index, asyh);  in nv50_dac_enable()
374 	asyh->or.depth = 0;  in nv50_dac_enable()
1285 		struct nv50_head_atom *asyh, u8 proto, u8 depth)  in nv50_sor_update()  argument
1290 	if (!asyh) {  in nv50_sor_update()
1297 		asyh->or.depth = depth;  in nv50_sor_update()
1300 	core->func->sor->ctrl(core, nv_encoder->or, nv_encoder->ctrl, asyh);  in nv50_sor_update()
1336 	struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);  in nv50_sor_enable()  local
1337 	struct drm_display_mode *mode = &asyh->state.adjusted_mode;  in nv50_sor_enable()
1431 	nv_encoder->update(nv_encoder, nv_crtc->index, asyh, proto, depth);  in nv50_sor_enable()
1559 	struct nv50_head_atom *asyh = nv50_head_atom(nv_crtc->base.state);  in nv50_pior_enable()  local
1568 	case 10: asyh->or.depth = 0x6; break;  in nv50_pior_enable()
1569 	case  8: asyh->or.depth = 0x5; break;  in nv50_pior_enable()
1570 	case  6: asyh->or.depth = 0x2; break;  in nv50_pior_enable()
1571 	default: asyh->or.depth = 0x0; break;  in nv50_pior_enable()
1584 	core->func->pior->ctrl(core, nv_encoder->or, (proto << 8) | owner, asyh);  in nv50_pior_enable()
1731 		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);  in nv50_disp_atomic_commit_tail()  local
1735 			  asyh->clr.mask, asyh->set.mask);  in nv50_disp_atomic_commit_tail()
1739 		if (asyh->clr.mask) {  in nv50_disp_atomic_commit_tail()
1740 			nv50_head_flush_clr(head, asyh, atom->flush_disable);  in nv50_disp_atomic_commit_tail()
1811 		struct nv50_head_atom *asyh = nv50_head_atom(new_crtc_state);  in nv50_disp_atomic_commit_tail()  local
1815 			  asyh->set.mask, asyh->clr.mask);  in nv50_disp_atomic_commit_tail()
1817 		if (asyh->set.mask) {  in nv50_disp_atomic_commit_tail()
1818 			nv50_head_flush_set(head, asyh);  in nv50_disp_atomic_commit_tail()