Lines Matching refs:ctrl
151 static int edp_clk_init(struct edp_ctrl *ctrl) in edp_clk_init() argument
153 struct platform_device *pdev = ctrl->pdev; in edp_clk_init()
156 ctrl->aux_clk = msm_clk_get(pdev, "core"); in edp_clk_init()
157 if (IS_ERR(ctrl->aux_clk)) { in edp_clk_init()
158 ret = PTR_ERR(ctrl->aux_clk); in edp_clk_init()
160 ctrl->aux_clk = NULL; in edp_clk_init()
164 ctrl->pixel_clk = msm_clk_get(pdev, "pixel"); in edp_clk_init()
165 if (IS_ERR(ctrl->pixel_clk)) { in edp_clk_init()
166 ret = PTR_ERR(ctrl->pixel_clk); in edp_clk_init()
168 ctrl->pixel_clk = NULL; in edp_clk_init()
172 ctrl->ahb_clk = msm_clk_get(pdev, "iface"); in edp_clk_init()
173 if (IS_ERR(ctrl->ahb_clk)) { in edp_clk_init()
174 ret = PTR_ERR(ctrl->ahb_clk); in edp_clk_init()
176 ctrl->ahb_clk = NULL; in edp_clk_init()
180 ctrl->link_clk = msm_clk_get(pdev, "link"); in edp_clk_init()
181 if (IS_ERR(ctrl->link_clk)) { in edp_clk_init()
182 ret = PTR_ERR(ctrl->link_clk); in edp_clk_init()
184 ctrl->link_clk = NULL; in edp_clk_init()
189 ctrl->mdp_core_clk = msm_clk_get(pdev, "mdp_core"); in edp_clk_init()
190 if (IS_ERR(ctrl->mdp_core_clk)) { in edp_clk_init()
191 ret = PTR_ERR(ctrl->mdp_core_clk); in edp_clk_init()
193 ctrl->mdp_core_clk = NULL; in edp_clk_init()
200 static int edp_clk_enable(struct edp_ctrl *ctrl, u32 clk_mask) in edp_clk_enable() argument
207 ret = clk_prepare_enable(ctrl->ahb_clk); in edp_clk_enable()
214 ret = clk_set_rate(ctrl->aux_clk, 19200000); in edp_clk_enable()
219 ret = clk_prepare_enable(ctrl->aux_clk); in edp_clk_enable()
228 (unsigned long)ctrl->link_rate * 27000000); in edp_clk_enable()
229 ret = clk_set_rate(ctrl->link_clk, in edp_clk_enable()
230 (unsigned long)ctrl->link_rate * 27000000); in edp_clk_enable()
237 ret = clk_prepare_enable(ctrl->link_clk); in edp_clk_enable()
245 (unsigned long)ctrl->pixel_rate * 1000); in edp_clk_enable()
246 ret = clk_set_rate(ctrl->pixel_clk, in edp_clk_enable()
247 (unsigned long)ctrl->pixel_rate * 1000); in edp_clk_enable()
254 ret = clk_prepare_enable(ctrl->pixel_clk); in edp_clk_enable()
261 ret = clk_prepare_enable(ctrl->mdp_core_clk); in edp_clk_enable()
272 clk_disable_unprepare(ctrl->pixel_clk); in edp_clk_enable()
275 clk_disable_unprepare(ctrl->link_clk); in edp_clk_enable()
278 clk_disable_unprepare(ctrl->aux_clk); in edp_clk_enable()
281 clk_disable_unprepare(ctrl->ahb_clk); in edp_clk_enable()
286 static void edp_clk_disable(struct edp_ctrl *ctrl, u32 clk_mask) in edp_clk_disable() argument
289 clk_disable_unprepare(ctrl->mdp_core_clk); in edp_clk_disable()
291 clk_disable_unprepare(ctrl->pixel_clk); in edp_clk_disable()
293 clk_disable_unprepare(ctrl->link_clk); in edp_clk_disable()
295 clk_disable_unprepare(ctrl->aux_clk); in edp_clk_disable()
297 clk_disable_unprepare(ctrl->ahb_clk); in edp_clk_disable()
300 static int edp_regulator_init(struct edp_ctrl *ctrl) in edp_regulator_init() argument
302 struct device *dev = &ctrl->pdev->dev; in edp_regulator_init()
306 ctrl->vdda_vreg = devm_regulator_get(dev, "vdda"); in edp_regulator_init()
307 ret = PTR_ERR_OR_ZERO(ctrl->vdda_vreg); in edp_regulator_init()
311 ctrl->vdda_vreg = NULL; in edp_regulator_init()
314 ctrl->lvl_vreg = devm_regulator_get(dev, "lvl-vdd"); in edp_regulator_init()
315 ret = PTR_ERR_OR_ZERO(ctrl->lvl_vreg); in edp_regulator_init()
319 ctrl->lvl_vreg = NULL; in edp_regulator_init()
326 static int edp_regulator_enable(struct edp_ctrl *ctrl) in edp_regulator_enable() argument
330 ret = regulator_set_load(ctrl->vdda_vreg, VDDA_UA_ON_LOAD); in edp_regulator_enable()
336 ret = regulator_enable(ctrl->vdda_vreg); in edp_regulator_enable()
342 ret = regulator_enable(ctrl->lvl_vreg); in edp_regulator_enable()
352 regulator_disable(ctrl->vdda_vreg); in edp_regulator_enable()
354 regulator_set_load(ctrl->vdda_vreg, VDDA_UA_OFF_LOAD); in edp_regulator_enable()
359 static void edp_regulator_disable(struct edp_ctrl *ctrl) in edp_regulator_disable() argument
361 regulator_disable(ctrl->lvl_vreg); in edp_regulator_disable()
362 regulator_disable(ctrl->vdda_vreg); in edp_regulator_disable()
363 regulator_set_load(ctrl->vdda_vreg, VDDA_UA_OFF_LOAD); in edp_regulator_disable()
366 static int edp_gpio_config(struct edp_ctrl *ctrl) in edp_gpio_config() argument
368 struct device *dev = &ctrl->pdev->dev; in edp_gpio_config()
371 ctrl->panel_hpd_gpio = devm_gpiod_get(dev, "panel-hpd", GPIOD_IN); in edp_gpio_config()
372 if (IS_ERR(ctrl->panel_hpd_gpio)) { in edp_gpio_config()
373 ret = PTR_ERR(ctrl->panel_hpd_gpio); in edp_gpio_config()
374 ctrl->panel_hpd_gpio = NULL; in edp_gpio_config()
379 ctrl->panel_en_gpio = devm_gpiod_get(dev, "panel-en", GPIOD_OUT_LOW); in edp_gpio_config()
380 if (IS_ERR(ctrl->panel_en_gpio)) { in edp_gpio_config()
381 ret = PTR_ERR(ctrl->panel_en_gpio); in edp_gpio_config()
382 ctrl->panel_en_gpio = NULL; in edp_gpio_config()
392 static void edp_ctrl_irq_enable(struct edp_ctrl *ctrl, int enable) in edp_ctrl_irq_enable() argument
397 spin_lock_irqsave(&ctrl->irq_lock, flags); in edp_ctrl_irq_enable()
399 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, EDP_INTR_MASK1); in edp_ctrl_irq_enable()
400 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, EDP_INTR_MASK2); in edp_ctrl_irq_enable()
402 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, 0x0); in edp_ctrl_irq_enable()
403 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, 0x0); in edp_ctrl_irq_enable()
405 spin_unlock_irqrestore(&ctrl->irq_lock, flags); in edp_ctrl_irq_enable()
409 static void edp_fill_link_cfg(struct edp_ctrl *ctrl) in edp_fill_link_cfg() argument
414 u8 max_lane = ctrl->dp_link.num_lanes; in edp_fill_link_cfg()
417 prate = ctrl->pixel_rate; in edp_fill_link_cfg()
418 bpp = ctrl->color_depth * 3; in edp_fill_link_cfg()
424 ctrl->link_rate = drm_dp_link_rate_to_bw_code(ctrl->dp_link.rate); in edp_fill_link_cfg()
430 lrate *= ctrl->link_rate; in edp_fill_link_cfg()
439 ctrl->lane_cnt = lane; in edp_fill_link_cfg()
440 DBG("rate=%d lane=%d", ctrl->link_rate, ctrl->lane_cnt); in edp_fill_link_cfg()
443 static void edp_config_ctrl(struct edp_ctrl *ctrl) in edp_config_ctrl() argument
448 data = EDP_CONFIGURATION_CTRL_LANES(ctrl->lane_cnt - 1); in edp_config_ctrl()
450 if (ctrl->dp_link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) in edp_config_ctrl()
454 if (ctrl->color_depth == 8) in edp_config_ctrl()
459 if (!ctrl->interlaced) /* progressive */ in edp_config_ctrl()
465 edp_write(ctrl->base + REG_EDP_CONFIGURATION_CTRL, data); in edp_config_ctrl()
468 static void edp_state_ctrl(struct edp_ctrl *ctrl, u32 state) in edp_state_ctrl() argument
470 edp_write(ctrl->base + REG_EDP_STATE_CTRL, state); in edp_state_ctrl()
475 static int edp_lane_set_write(struct edp_ctrl *ctrl, in edp_lane_set_write() argument
493 if (drm_dp_dpcd_write(ctrl->drm_aux, 0x103, buf, 4) < 4) { in edp_lane_set_write()
501 static int edp_train_pattern_set_write(struct edp_ctrl *ctrl, u8 pattern) in edp_train_pattern_set_write() argument
506 if (drm_dp_dpcd_write(ctrl->drm_aux, in edp_train_pattern_set_write()
515 static void edp_sink_train_set_adjust(struct edp_ctrl *ctrl, in edp_sink_train_set_adjust() argument
523 for (i = 0; i < ctrl->lane_cnt; i++) { in edp_sink_train_set_adjust()
530 ctrl->v_level = max >> DP_TRAIN_VOLTAGE_SWING_SHIFT; in edp_sink_train_set_adjust()
534 for (i = 0; i < ctrl->lane_cnt; i++) { in edp_sink_train_set_adjust()
541 ctrl->p_level = max >> DP_TRAIN_PRE_EMPHASIS_SHIFT; in edp_sink_train_set_adjust()
542 DBG("v_level=%d, p_level=%d", ctrl->v_level, ctrl->p_level); in edp_sink_train_set_adjust()
545 static void edp_host_train_set(struct edp_ctrl *ctrl, u32 train) in edp_host_train_set() argument
553 edp_state_ctrl(ctrl, EDP_STATE_CTRL_TRAIN_PATTERN_1 << shift); in edp_host_train_set()
555 data = edp_read(ctrl->base + REG_EDP_MAINLINK_READY); in edp_host_train_set()
579 static int edp_voltage_pre_emphasise_set(struct edp_ctrl *ctrl) in edp_voltage_pre_emphasise_set() argument
584 DBG("v=%d p=%d", ctrl->v_level, ctrl->p_level); in edp_voltage_pre_emphasise_set()
586 value0 = vm_pre_emphasis[(int)(ctrl->v_level)][(int)(ctrl->p_level)]; in edp_voltage_pre_emphasise_set()
587 value1 = vm_voltage_swing[(int)(ctrl->v_level)][(int)(ctrl->p_level)]; in edp_voltage_pre_emphasise_set()
591 msm_edp_phy_vm_pe_cfg(ctrl->phy, value0, value1); in edp_voltage_pre_emphasise_set()
592 return edp_lane_set_write(ctrl, ctrl->v_level, ctrl->p_level); in edp_voltage_pre_emphasise_set()
598 static int edp_start_link_train_1(struct edp_ctrl *ctrl) in edp_start_link_train_1() argument
608 edp_host_train_set(ctrl, DP_TRAINING_PATTERN_1); in edp_start_link_train_1()
609 ret = edp_voltage_pre_emphasise_set(ctrl); in edp_start_link_train_1()
612 ret = edp_train_pattern_set_write(ctrl, in edp_start_link_train_1()
618 old_v_level = ctrl->v_level; in edp_start_link_train_1()
620 drm_dp_link_train_clock_recovery_delay(ctrl->dpcd); in edp_start_link_train_1()
622 rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); in edp_start_link_train_1()
627 if (drm_dp_clock_recovery_ok(link_status, ctrl->lane_cnt)) { in edp_start_link_train_1()
632 if (ctrl->v_level == DPCD_LINK_VOLTAGE_MAX) { in edp_start_link_train_1()
637 if (old_v_level == ctrl->v_level) { in edp_start_link_train_1()
645 old_v_level = ctrl->v_level; in edp_start_link_train_1()
648 edp_sink_train_set_adjust(ctrl, link_status); in edp_start_link_train_1()
649 ret = edp_voltage_pre_emphasise_set(ctrl); in edp_start_link_train_1()
657 static int edp_start_link_train_2(struct edp_ctrl *ctrl) in edp_start_link_train_2() argument
666 edp_host_train_set(ctrl, DP_TRAINING_PATTERN_2); in edp_start_link_train_2()
667 ret = edp_voltage_pre_emphasise_set(ctrl); in edp_start_link_train_2()
671 ret = edp_train_pattern_set_write(ctrl, in edp_start_link_train_2()
677 drm_dp_link_train_channel_eq_delay(ctrl->dpcd); in edp_start_link_train_2()
679 rlen = drm_dp_dpcd_read_link_status(ctrl->drm_aux, link_status); in edp_start_link_train_2()
684 if (drm_dp_channel_eq_ok(link_status, ctrl->lane_cnt)) { in edp_start_link_train_2()
695 edp_sink_train_set_adjust(ctrl, link_status); in edp_start_link_train_2()
696 ret = edp_voltage_pre_emphasise_set(ctrl); in edp_start_link_train_2()
704 static int edp_link_rate_down_shift(struct edp_ctrl *ctrl) in edp_link_rate_down_shift() argument
710 rate = ctrl->link_rate; in edp_link_rate_down_shift()
711 lane = ctrl->lane_cnt; in edp_link_rate_down_shift()
712 max_lane = ctrl->dp_link.num_lanes; in edp_link_rate_down_shift()
714 bpp = ctrl->color_depth * 3; in edp_link_rate_down_shift()
715 prate = ctrl->pixel_rate; in edp_link_rate_down_shift()
735 ctrl->pixel_rate, in edp_link_rate_down_shift()
739 ctrl->link_rate = rate; in edp_link_rate_down_shift()
740 ctrl->lane_cnt = lane; in edp_link_rate_down_shift()
749 static int edp_clear_training_pattern(struct edp_ctrl *ctrl) in edp_clear_training_pattern() argument
753 ret = edp_train_pattern_set_write(ctrl, 0); in edp_clear_training_pattern()
755 drm_dp_link_train_channel_eq_delay(ctrl->dpcd); in edp_clear_training_pattern()
760 static int edp_do_link_train(struct edp_ctrl *ctrl) in edp_do_link_train() argument
770 dp_link.num_lanes = ctrl->lane_cnt; in edp_do_link_train()
771 dp_link.rate = drm_dp_bw_code_to_link_rate(ctrl->link_rate); in edp_do_link_train()
772 dp_link.capabilities = ctrl->dp_link.capabilities; in edp_do_link_train()
773 if (drm_dp_link_configure(ctrl->drm_aux, &dp_link) < 0) in edp_do_link_train()
776 ctrl->v_level = 0; /* start from default level */ in edp_do_link_train()
777 ctrl->p_level = 0; in edp_do_link_train()
779 edp_state_ctrl(ctrl, 0); in edp_do_link_train()
780 if (edp_clear_training_pattern(ctrl)) in edp_do_link_train()
783 ret = edp_start_link_train_1(ctrl); in edp_do_link_train()
785 if (edp_link_rate_down_shift(ctrl) == 0) { in edp_do_link_train()
797 edp_state_ctrl(ctrl, 0); in edp_do_link_train()
798 if (edp_clear_training_pattern(ctrl)) in edp_do_link_train()
801 ret = edp_start_link_train_2(ctrl); in edp_do_link_train()
803 if (edp_link_rate_down_shift(ctrl) == 0) { in edp_do_link_train()
815 edp_state_ctrl(ctrl, EDP_STATE_CTRL_SEND_VIDEO); in edp_do_link_train()
817 edp_clear_training_pattern(ctrl); in edp_do_link_train()
822 static void edp_clock_synchrous(struct edp_ctrl *ctrl, int sync) in edp_clock_synchrous() argument
827 data = edp_read(ctrl->base + REG_EDP_MISC1_MISC0); in edp_clock_synchrous()
836 if (ctrl->color_depth == 8) in edp_clock_synchrous()
838 else if (ctrl->color_depth == 10) in edp_clock_synchrous()
840 else if (ctrl->color_depth == 12) in edp_clock_synchrous()
842 else if (ctrl->color_depth == 16) in edp_clock_synchrous()
847 edp_write(ctrl->base + REG_EDP_MISC1_MISC0, data); in edp_clock_synchrous()
850 static int edp_sw_mvid_nvid(struct edp_ctrl *ctrl, u32 m, u32 n) in edp_sw_mvid_nvid() argument
854 if (ctrl->link_rate == DP_LINK_BW_1_62) { in edp_sw_mvid_nvid()
856 } else if (ctrl->link_rate == DP_LINK_BW_2_7) { in edp_sw_mvid_nvid()
860 ctrl->link_rate); in edp_sw_mvid_nvid()
864 edp_write(ctrl->base + REG_EDP_SOFTWARE_MVID, m * m_multi); in edp_sw_mvid_nvid()
865 edp_write(ctrl->base + REG_EDP_SOFTWARE_NVID, n * n_multi); in edp_sw_mvid_nvid()
870 static void edp_mainlink_ctrl(struct edp_ctrl *ctrl, int enable) in edp_mainlink_ctrl() argument
874 edp_write(ctrl->base + REG_EDP_MAINLINK_CTRL, EDP_MAINLINK_CTRL_RESET); in edp_mainlink_ctrl()
882 edp_write(ctrl->base + REG_EDP_MAINLINK_CTRL, data); in edp_mainlink_ctrl()
885 static void edp_ctrl_phy_aux_enable(struct edp_ctrl *ctrl, int enable) in edp_ctrl_phy_aux_enable() argument
888 edp_regulator_enable(ctrl); in edp_ctrl_phy_aux_enable()
889 edp_clk_enable(ctrl, EDP_CLK_MASK_AUX_CHAN); in edp_ctrl_phy_aux_enable()
890 msm_edp_phy_ctrl(ctrl->phy, 1); in edp_ctrl_phy_aux_enable()
891 msm_edp_aux_ctrl(ctrl->aux, 1); in edp_ctrl_phy_aux_enable()
892 gpiod_set_value(ctrl->panel_en_gpio, 1); in edp_ctrl_phy_aux_enable()
894 gpiod_set_value(ctrl->panel_en_gpio, 0); in edp_ctrl_phy_aux_enable()
895 msm_edp_aux_ctrl(ctrl->aux, 0); in edp_ctrl_phy_aux_enable()
896 msm_edp_phy_ctrl(ctrl->phy, 0); in edp_ctrl_phy_aux_enable()
897 edp_clk_disable(ctrl, EDP_CLK_MASK_AUX_CHAN); in edp_ctrl_phy_aux_enable()
898 edp_regulator_disable(ctrl); in edp_ctrl_phy_aux_enable()
902 static void edp_ctrl_link_enable(struct edp_ctrl *ctrl, int enable) in edp_ctrl_link_enable() argument
908 edp_clk_enable(ctrl, EDP_CLK_MASK_LINK_CHAN); in edp_ctrl_link_enable()
910 msm_edp_phy_lane_power_ctrl(ctrl->phy, true, ctrl->lane_cnt); in edp_ctrl_link_enable()
912 msm_edp_phy_vm_pe_init(ctrl->phy); in edp_ctrl_link_enable()
916 msm_edp_phy_ready(ctrl->phy); in edp_ctrl_link_enable()
918 edp_config_ctrl(ctrl); in edp_ctrl_link_enable()
919 msm_edp_ctrl_pixel_clock_valid(ctrl, ctrl->pixel_rate, &m, &n); in edp_ctrl_link_enable()
920 edp_sw_mvid_nvid(ctrl, m, n); in edp_ctrl_link_enable()
921 edp_mainlink_ctrl(ctrl, 1); in edp_ctrl_link_enable()
923 edp_mainlink_ctrl(ctrl, 0); in edp_ctrl_link_enable()
925 msm_edp_phy_lane_power_ctrl(ctrl->phy, false, 0); in edp_ctrl_link_enable()
926 edp_clk_disable(ctrl, EDP_CLK_MASK_LINK_CHAN); in edp_ctrl_link_enable()
930 static int edp_ctrl_training(struct edp_ctrl *ctrl) in edp_ctrl_training() argument
935 if (!ctrl->power_on) in edp_ctrl_training()
939 ret = edp_do_link_train(ctrl); in edp_ctrl_training()
942 edp_ctrl_irq_enable(ctrl, 0); in edp_ctrl_training()
943 edp_ctrl_link_enable(ctrl, 0); in edp_ctrl_training()
944 msm_edp_phy_ctrl(ctrl->phy, 0); in edp_ctrl_training()
950 msm_edp_phy_ctrl(ctrl->phy, 1); in edp_ctrl_training()
951 edp_ctrl_link_enable(ctrl, 1); in edp_ctrl_training()
952 edp_ctrl_irq_enable(ctrl, 1); in edp_ctrl_training()
961 struct edp_ctrl *ctrl = container_of( in edp_ctrl_on_worker() local
965 mutex_lock(&ctrl->dev_mutex); in edp_ctrl_on_worker()
967 if (ctrl->power_on) { in edp_ctrl_on_worker()
972 edp_ctrl_phy_aux_enable(ctrl, 1); in edp_ctrl_on_worker()
973 edp_ctrl_link_enable(ctrl, 1); in edp_ctrl_on_worker()
975 edp_ctrl_irq_enable(ctrl, 1); in edp_ctrl_on_worker()
976 ret = drm_dp_link_power_up(ctrl->drm_aux, &ctrl->dp_link); in edp_ctrl_on_worker()
980 ctrl->power_on = true; in edp_ctrl_on_worker()
983 ret = edp_ctrl_training(ctrl); in edp_ctrl_on_worker()
991 edp_ctrl_irq_enable(ctrl, 0); in edp_ctrl_on_worker()
992 edp_ctrl_link_enable(ctrl, 0); in edp_ctrl_on_worker()
993 edp_ctrl_phy_aux_enable(ctrl, 0); in edp_ctrl_on_worker()
994 ctrl->power_on = false; in edp_ctrl_on_worker()
996 mutex_unlock(&ctrl->dev_mutex); in edp_ctrl_on_worker()
1001 struct edp_ctrl *ctrl = container_of( in edp_ctrl_off_worker() local
1005 mutex_lock(&ctrl->dev_mutex); in edp_ctrl_off_worker()
1007 if (!ctrl->power_on) { in edp_ctrl_off_worker()
1012 reinit_completion(&ctrl->idle_comp); in edp_ctrl_off_worker()
1013 edp_state_ctrl(ctrl, EDP_STATE_CTRL_PUSH_IDLE); in edp_ctrl_off_worker()
1015 time_left = wait_for_completion_timeout(&ctrl->idle_comp, in edp_ctrl_off_worker()
1020 edp_state_ctrl(ctrl, 0); in edp_ctrl_off_worker()
1022 drm_dp_link_power_down(ctrl->drm_aux, &ctrl->dp_link); in edp_ctrl_off_worker()
1024 edp_ctrl_irq_enable(ctrl, 0); in edp_ctrl_off_worker()
1026 edp_ctrl_link_enable(ctrl, 0); in edp_ctrl_off_worker()
1028 edp_ctrl_phy_aux_enable(ctrl, 0); in edp_ctrl_off_worker()
1030 ctrl->power_on = false; in edp_ctrl_off_worker()
1033 mutex_unlock(&ctrl->dev_mutex); in edp_ctrl_off_worker()
1036 irqreturn_t msm_edp_ctrl_irq(struct edp_ctrl *ctrl) in msm_edp_ctrl_irq() argument
1042 spin_lock(&ctrl->irq_lock); in msm_edp_ctrl_irq()
1043 isr1 = edp_read(ctrl->base + REG_EDP_INTERRUPT_REG_1); in msm_edp_ctrl_irq()
1044 isr2 = edp_read(ctrl->base + REG_EDP_INTERRUPT_REG_2); in msm_edp_ctrl_irq()
1058 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_1, ack); in msm_edp_ctrl_irq()
1063 edp_write(ctrl->base + REG_EDP_INTERRUPT_REG_2, ack); in msm_edp_ctrl_irq()
1064 spin_unlock(&ctrl->irq_lock); in msm_edp_ctrl_irq()
1074 complete(&ctrl->idle_comp); in msm_edp_ctrl_irq()
1077 msm_edp_aux_irq(ctrl->aux, isr1); in msm_edp_ctrl_irq()
1082 void msm_edp_ctrl_power(struct edp_ctrl *ctrl, bool on) in msm_edp_ctrl_power() argument
1085 queue_work(ctrl->workqueue, &ctrl->on_work); in msm_edp_ctrl_power()
1087 queue_work(ctrl->workqueue, &ctrl->off_work); in msm_edp_ctrl_power()
1092 struct edp_ctrl *ctrl = NULL; in msm_edp_ctrl_init() local
1101 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); in msm_edp_ctrl_init()
1102 if (!ctrl) in msm_edp_ctrl_init()
1105 edp->ctrl = ctrl; in msm_edp_ctrl_init()
1106 ctrl->pdev = edp->pdev; in msm_edp_ctrl_init()
1108 ctrl->base = msm_ioremap(ctrl->pdev, "edp", "eDP"); in msm_edp_ctrl_init()
1109 if (IS_ERR(ctrl->base)) in msm_edp_ctrl_init()
1110 return PTR_ERR(ctrl->base); in msm_edp_ctrl_init()
1113 ret = edp_regulator_init(ctrl); in msm_edp_ctrl_init()
1118 ret = edp_clk_init(ctrl); in msm_edp_ctrl_init()
1123 ret = edp_gpio_config(ctrl); in msm_edp_ctrl_init()
1130 ctrl->aux = msm_edp_aux_init(dev, ctrl->base, &ctrl->drm_aux); in msm_edp_ctrl_init()
1131 if (!ctrl->aux || !ctrl->drm_aux) { in msm_edp_ctrl_init()
1136 ctrl->phy = msm_edp_phy_init(dev, ctrl->base); in msm_edp_ctrl_init()
1137 if (!ctrl->phy) { in msm_edp_ctrl_init()
1143 spin_lock_init(&ctrl->irq_lock); in msm_edp_ctrl_init()
1144 mutex_init(&ctrl->dev_mutex); in msm_edp_ctrl_init()
1145 init_completion(&ctrl->idle_comp); in msm_edp_ctrl_init()
1148 ctrl->workqueue = alloc_ordered_workqueue("edp_drm_work", 0); in msm_edp_ctrl_init()
1149 INIT_WORK(&ctrl->on_work, edp_ctrl_on_worker); in msm_edp_ctrl_init()
1150 INIT_WORK(&ctrl->off_work, edp_ctrl_off_worker); in msm_edp_ctrl_init()
1155 msm_edp_aux_destroy(dev, ctrl->aux); in msm_edp_ctrl_init()
1156 ctrl->aux = NULL; in msm_edp_ctrl_init()
1160 void msm_edp_ctrl_destroy(struct edp_ctrl *ctrl) in msm_edp_ctrl_destroy() argument
1162 if (!ctrl) in msm_edp_ctrl_destroy()
1165 if (ctrl->workqueue) { in msm_edp_ctrl_destroy()
1166 flush_workqueue(ctrl->workqueue); in msm_edp_ctrl_destroy()
1167 destroy_workqueue(ctrl->workqueue); in msm_edp_ctrl_destroy()
1168 ctrl->workqueue = NULL; in msm_edp_ctrl_destroy()
1171 if (ctrl->aux) { in msm_edp_ctrl_destroy()
1172 msm_edp_aux_destroy(&ctrl->pdev->dev, ctrl->aux); in msm_edp_ctrl_destroy()
1173 ctrl->aux = NULL; in msm_edp_ctrl_destroy()
1176 kfree(ctrl->edid); in msm_edp_ctrl_destroy()
1177 ctrl->edid = NULL; in msm_edp_ctrl_destroy()
1179 mutex_destroy(&ctrl->dev_mutex); in msm_edp_ctrl_destroy()
1182 bool msm_edp_ctrl_panel_connected(struct edp_ctrl *ctrl) in msm_edp_ctrl_panel_connected() argument
1184 mutex_lock(&ctrl->dev_mutex); in msm_edp_ctrl_panel_connected()
1185 DBG("connect status = %d", ctrl->edp_connected); in msm_edp_ctrl_panel_connected()
1186 if (ctrl->edp_connected) { in msm_edp_ctrl_panel_connected()
1187 mutex_unlock(&ctrl->dev_mutex); in msm_edp_ctrl_panel_connected()
1191 if (!ctrl->power_on) { in msm_edp_ctrl_panel_connected()
1192 edp_ctrl_phy_aux_enable(ctrl, 1); in msm_edp_ctrl_panel_connected()
1193 edp_ctrl_irq_enable(ctrl, 1); in msm_edp_ctrl_panel_connected()
1196 if (drm_dp_dpcd_read(ctrl->drm_aux, DP_DPCD_REV, ctrl->dpcd, in msm_edp_ctrl_panel_connected()
1199 memset(ctrl->dpcd, 0, DP_RECEIVER_CAP_SIZE); in msm_edp_ctrl_panel_connected()
1201 ctrl->edp_connected = true; in msm_edp_ctrl_panel_connected()
1204 if (!ctrl->power_on) { in msm_edp_ctrl_panel_connected()
1205 edp_ctrl_irq_enable(ctrl, 0); in msm_edp_ctrl_panel_connected()
1206 edp_ctrl_phy_aux_enable(ctrl, 0); in msm_edp_ctrl_panel_connected()
1209 DBG("exit: connect status=%d", ctrl->edp_connected); in msm_edp_ctrl_panel_connected()
1211 mutex_unlock(&ctrl->dev_mutex); in msm_edp_ctrl_panel_connected()
1213 return ctrl->edp_connected; in msm_edp_ctrl_panel_connected()
1216 int msm_edp_ctrl_get_panel_info(struct edp_ctrl *ctrl, in msm_edp_ctrl_get_panel_info() argument
1221 mutex_lock(&ctrl->dev_mutex); in msm_edp_ctrl_get_panel_info()
1223 if (ctrl->edid) { in msm_edp_ctrl_get_panel_info()
1226 *edid = ctrl->edid; in msm_edp_ctrl_get_panel_info()
1231 if (!ctrl->power_on) { in msm_edp_ctrl_get_panel_info()
1232 edp_ctrl_phy_aux_enable(ctrl, 1); in msm_edp_ctrl_get_panel_info()
1233 edp_ctrl_irq_enable(ctrl, 1); in msm_edp_ctrl_get_panel_info()
1236 ret = drm_dp_link_probe(ctrl->drm_aux, &ctrl->dp_link); in msm_edp_ctrl_get_panel_info()
1243 ctrl->link_rate = drm_dp_link_rate_to_bw_code(ctrl->dp_link.rate); in msm_edp_ctrl_get_panel_info()
1245 ctrl->edid = drm_get_edid(connector, &ctrl->drm_aux->ddc); in msm_edp_ctrl_get_panel_info()
1246 if (!ctrl->edid) { in msm_edp_ctrl_get_panel_info()
1252 *edid = ctrl->edid; in msm_edp_ctrl_get_panel_info()
1255 if (!ctrl->power_on) { in msm_edp_ctrl_get_panel_info()
1256 edp_ctrl_irq_enable(ctrl, 0); in msm_edp_ctrl_get_panel_info()
1257 edp_ctrl_phy_aux_enable(ctrl, 0); in msm_edp_ctrl_get_panel_info()
1260 mutex_unlock(&ctrl->dev_mutex); in msm_edp_ctrl_get_panel_info()
1264 int msm_edp_ctrl_timing_cfg(struct edp_ctrl *ctrl, in msm_edp_ctrl_timing_cfg() argument
1272 mutex_lock(&ctrl->dev_mutex); in msm_edp_ctrl_timing_cfg()
1277 ctrl->color_depth = info->bpc; in msm_edp_ctrl_timing_cfg()
1278 ctrl->pixel_rate = mode->clock; in msm_edp_ctrl_timing_cfg()
1279 ctrl->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); in msm_edp_ctrl_timing_cfg()
1282 edp_fill_link_cfg(ctrl); in msm_edp_ctrl_timing_cfg()
1284 if (edp_clk_enable(ctrl, EDP_CLK_MASK_AHB)) { in msm_edp_ctrl_timing_cfg()
1289 edp_clock_synchrous(ctrl, 1); in msm_edp_ctrl_timing_cfg()
1292 edp_write(ctrl->base + REG_EDP_TOTAL_HOR_VER, in msm_edp_ctrl_timing_cfg()
1298 edp_write(ctrl->base + REG_EDP_START_HOR_VER_FROM_SYNC, in msm_edp_ctrl_timing_cfg()
1310 edp_write(ctrl->base + REG_EDP_HSYNC_VSYNC_WIDTH_POLARITY, data); in msm_edp_ctrl_timing_cfg()
1312 edp_write(ctrl->base + REG_EDP_ACTIVE_HOR_VER, in msm_edp_ctrl_timing_cfg()
1316 edp_clk_disable(ctrl, EDP_CLK_MASK_AHB); in msm_edp_ctrl_timing_cfg()
1319 mutex_unlock(&ctrl->dev_mutex); in msm_edp_ctrl_timing_cfg()
1323 bool msm_edp_ctrl_pixel_clock_valid(struct edp_ctrl *ctrl, in msm_edp_ctrl_pixel_clock_valid() argument
1331 if (ctrl->link_rate == DP_LINK_BW_1_62) { in msm_edp_ctrl_pixel_clock_valid()
1333 } else if (ctrl->link_rate == DP_LINK_BW_2_7) { in msm_edp_ctrl_pixel_clock_valid()
1336 pr_err("%s: Invalid link rate,%d\n", __func__, ctrl->link_rate); in msm_edp_ctrl_pixel_clock_valid()