196 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)  in dsi_write()  function
783 	dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);  in dsi_intr_ctrl()
830 		dsi_write(msm_host, REG_DSI_CTRL, 0);  in dsi_ctrl_config()
851 		dsi_write(msm_host, REG_DSI_VID_CFG0, data);  in dsi_ctrl_config()
855 		dsi_write(msm_host, REG_DSI_VID_CFG1, 0);  in dsi_ctrl_config()
860 		dsi_write(msm_host, REG_DSI_CMD_CFG0, data);  in dsi_ctrl_config()
867 		dsi_write(msm_host, REG_DSI_CMD_CFG1, data);  in dsi_ctrl_config()
870 	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,  in dsi_ctrl_config()
883 	dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);  in dsi_ctrl_config()
887 	dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);  in dsi_ctrl_config()
892 		dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,  in dsi_ctrl_config()
898 	dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);  in dsi_ctrl_config()
901 	dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);  in dsi_ctrl_config()
905 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_ctrl_config()
912 	dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,  in dsi_ctrl_config()
916 		dsi_write(msm_host, REG_DSI_LANE_CTRL,  in dsi_ctrl_config()
921 	dsi_write(msm_host, REG_DSI_CTRL, data);  in dsi_ctrl_config()
957 		dsi_write(msm_host, REG_DSI_ACTIVE_H,  in dsi_timing_setup()
960 		dsi_write(msm_host, REG_DSI_ACTIVE_V,  in dsi_timing_setup()
963 		dsi_write(msm_host, REG_DSI_TOTAL,  in dsi_timing_setup()
967 		dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,  in dsi_timing_setup()
970 		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);  in dsi_timing_setup()
971 		dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,  in dsi_timing_setup()
978 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL,  in dsi_timing_setup()
985 		dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL,  in dsi_timing_setup()
993 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_sw_reset()
996 	dsi_write(msm_host, REG_DSI_RESET, 1);  in dsi_sw_reset()
998 	dsi_write(msm_host, REG_DSI_RESET, 0);  in dsi_sw_reset()
1023 	dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);  in dsi_op_mode_config()
1037 	dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);  in dsi_set_tx_power_mode()
1393 	dsi_write(msm_host, REG_DSI_CTRL, data1);  in dsi_sw_reset_restore()
1400 	dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);  in dsi_sw_reset_restore()
1404 	dsi_write(msm_host, REG_DSI_RESET, 1);  in dsi_sw_reset_restore()
1406 	dsi_write(msm_host, REG_DSI_RESET, 0);  in dsi_sw_reset_restore()
1408 	dsi_write(msm_host, REG_DSI_CTRL, data0);  in dsi_sw_reset_restore()
1444 		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);  in dsi_ack_err_status()
1446 		dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);  in dsi_ack_err_status()
1458 		dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);  in dsi_timeout_status()
1474 		dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);  in dsi_dln0_phy_err()
1487 		dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);  in dsi_fifo_status()
1502 		dsi_write(msm_host, REG_DSI_STATUS0, status);  in dsi_status()
1515 		dsi_write(msm_host, REG_DSI_CLK_STATUS, status);  in dsi_clk_status()
1546 	dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);  in dsi_host_irq()
2012 	dsi_write(msm_host, REG_DSI_CTRL,  in msm_dsi_host_xfer_prepare()
2028 	dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);  in msm_dsi_host_xfer_restore()
2096 			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,  in msm_dsi_host_cmd_rx()
2099 			dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);  in msm_dsi_host_cmd_rx()
2187 	dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);  in msm_dsi_host_cmd_xfer_commit()
2188 	dsi_write(msm_host, REG_DSI_DMA_LEN, len);  in msm_dsi_host_cmd_xfer_commit()
2189 	dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);  in msm_dsi_host_cmd_xfer_commit()
2251 	dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);  in msm_dsi_host_reset_phy()
2255 	dsi_write(msm_host, REG_DSI_PHY_RESET, 0);  in msm_dsi_host_reset_phy()