Lines Matching refs:phys
466 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in dpu_encoder_get_hw_resources() local
468 if (phys && phys->ops.get_hw_resources) in dpu_encoder_get_hw_resources()
469 phys->ops.get_hw_resources(phys, hw_res, conn_state); in dpu_encoder_get_hw_resources()
489 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in dpu_encoder_destroy() local
491 if (phys && phys->ops.destroy) { in dpu_encoder_destroy()
492 phys->ops.destroy(phys); in dpu_encoder_destroy()
636 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in dpu_encoder_virt_atomic_check() local
638 if (phys && phys->ops.atomic_check) in dpu_encoder_virt_atomic_check()
639 ret = phys->ops.atomic_check(phys, crtc_state, in dpu_encoder_virt_atomic_check()
641 else if (phys && phys->ops.mode_fixup) in dpu_encoder_virt_atomic_check()
642 if (!phys->ops.mode_fixup(phys, mode, adj_mode)) in dpu_encoder_virt_atomic_check()
743 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in _dpu_encoder_irq_control() local
745 if (phys && phys->ops.irq_control) in _dpu_encoder_irq_control()
746 phys->ops.irq_control(phys, enable); in _dpu_encoder_irq_control()
1071 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in dpu_encoder_virt_mode_set() local
1073 if (phys) { in dpu_encoder_virt_mode_set()
1079 phys->hw_pp = dpu_enc->hw_pp[i]; in dpu_encoder_virt_mode_set()
1080 phys->connector = conn->state->connector; in dpu_encoder_virt_mode_set()
1081 phys->topology_name = topology_name; in dpu_encoder_virt_mode_set()
1082 if (phys->ops.mode_set) in dpu_encoder_virt_mode_set()
1083 phys->ops.mode_set(phys, mode, adj_mode); in dpu_encoder_virt_mode_set()
1141 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in dpu_encoder_virt_restore() local
1143 if (phys && (phys != dpu_enc->cur_master) && phys->ops.restore) in dpu_encoder_virt_restore()
1144 phys->ops.restore(phys); in dpu_encoder_virt_restore()
1171 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in dpu_encoder_virt_enable() local
1173 if (phys && phys->ops.is_master && phys->ops.is_master(phys)) { in dpu_encoder_virt_enable()
1175 dpu_enc->cur_master = phys; in dpu_encoder_virt_enable()
1193 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in dpu_encoder_virt_enable() local
1195 if (!phys) in dpu_encoder_virt_enable()
1198 if (phys != dpu_enc->cur_master) { in dpu_encoder_virt_enable()
1199 if (phys->ops.enable) in dpu_encoder_virt_enable()
1200 phys->ops.enable(phys); in dpu_encoder_virt_enable()
1204 MSM_DISPLAY_CAP_VID_MODE) && phys->ops.setup_misr) in dpu_encoder_virt_enable()
1205 phys->ops.setup_misr(phys, true, in dpu_encoder_virt_enable()
1250 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in dpu_encoder_virt_disable() local
1252 if (phys && phys->ops.disable) in dpu_encoder_virt_disable()
1253 phys->ops.disable(phys); in dpu_encoder_virt_disable()
1347 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in dpu_encoder_register_vblank_callback() local
1349 if (phys && phys->ops.control_vblank_irq) in dpu_encoder_register_vblank_callback()
1350 phys->ops.control_vblank_irq(phys, enable); in dpu_encoder_register_vblank_callback()
1449 struct dpu_encoder_phys *phys, uint32_t extra_flush_bits) in _dpu_encoder_trigger_flush() argument
1455 if (!drm_enc || !phys) { in _dpu_encoder_trigger_flush()
1457 drm_enc != 0, phys != 0); in _dpu_encoder_trigger_flush()
1461 if (!phys->hw_pp) { in _dpu_encoder_trigger_flush()
1466 ctl = phys->hw_ctl; in _dpu_encoder_trigger_flush()
1472 pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys); in _dpu_encoder_trigger_flush()
1482 trace_dpu_enc_trigger_flush(DRMID(drm_enc), phys->intf_idx, in _dpu_encoder_trigger_flush()
1490 static inline void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys) in _dpu_encoder_trigger_start() argument
1492 if (!phys) { in _dpu_encoder_trigger_start()
1497 if (!phys->hw_pp) { in _dpu_encoder_trigger_start()
1502 if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED) in _dpu_encoder_trigger_start()
1503 phys->ops.trigger_start(phys); in _dpu_encoder_trigger_start()
1602 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in _dpu_encoder_kickoff_phys() local
1604 if (!phys || phys->enable_state == DPU_ENC_DISABLED) in _dpu_encoder_kickoff_phys()
1607 ctl = phys->hw_ctl; in _dpu_encoder_kickoff_phys()
1611 if (phys->split_role != ENC_ROLE_SLAVE) in _dpu_encoder_kickoff_phys()
1613 if (!phys->ops.needs_single_flush || in _dpu_encoder_kickoff_phys()
1614 !phys->ops.needs_single_flush(phys)) in _dpu_encoder_kickoff_phys()
1615 _dpu_encoder_trigger_flush(&dpu_enc->base, phys, 0x0); in _dpu_encoder_kickoff_phys()
1636 struct dpu_encoder_phys *phys; in dpu_encoder_trigger_kickoff_pending() local
1649 phys = dpu_enc->phys_encs[i]; in dpu_encoder_trigger_kickoff_pending()
1651 if (phys && phys->hw_ctl) { in dpu_encoder_trigger_kickoff_pending()
1652 ctl = phys->hw_ctl; in dpu_encoder_trigger_kickoff_pending()
1657 if ((phys == dpu_enc->cur_master) && in dpu_encoder_trigger_kickoff_pending()
1812 struct dpu_encoder_phys *phys; in dpu_encoder_prepare_for_kickoff() local
1827 phys = dpu_enc->phys_encs[i]; in dpu_encoder_prepare_for_kickoff()
1828 if (phys) { in dpu_encoder_prepare_for_kickoff()
1829 if (phys->ops.prepare_for_kickoff) in dpu_encoder_prepare_for_kickoff()
1830 phys->ops.prepare_for_kickoff(phys, params); in dpu_encoder_prepare_for_kickoff()
1831 if (phys->enable_state == DPU_ENC_ERR_NEEDS_HW_RESET) in dpu_encoder_prepare_for_kickoff()
1843 phys = dpu_enc->phys_encs[i]; in dpu_encoder_prepare_for_kickoff()
1844 if (phys && phys->ops.hw_reset) in dpu_encoder_prepare_for_kickoff()
1845 phys->ops.hw_reset(phys); in dpu_encoder_prepare_for_kickoff()
1853 struct dpu_encoder_phys *phys; in dpu_encoder_kickoff() local
1877 phys = dpu_enc->phys_encs[i]; in dpu_encoder_kickoff()
1878 if (phys && phys->ops.handle_post_kickoff) in dpu_encoder_kickoff()
1879 phys->ops.handle_post_kickoff(phys); in dpu_encoder_kickoff()
1896 struct dpu_encoder_phys *phys; in dpu_encoder_prepare_commit() local
1906 phys = dpu_enc->phys_encs[i]; in dpu_encoder_prepare_commit()
1907 if (phys && phys->ops.prepare_commit) in dpu_encoder_prepare_commit()
1908 phys->ops.prepare_commit(phys); in dpu_encoder_prepare_commit()
1925 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in _dpu_encoder_status_show() local
1927 if (!phys) in _dpu_encoder_status_show()
1931 phys->intf_idx - INTF_0, in _dpu_encoder_status_show()
1932 atomic_read(&phys->vsync_cnt), in _dpu_encoder_status_show()
1933 atomic_read(&phys->underrun_cnt)); in _dpu_encoder_status_show()
1935 switch (phys->intf_mode) { in _dpu_encoder_status_show()
1989 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in _dpu_encoder_misr_setup() local
1991 if (!phys || !phys->ops.setup_misr) in _dpu_encoder_misr_setup()
1994 phys->ops.setup_misr(phys, enable, frame_count); in _dpu_encoder_misr_setup()
2035 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in _dpu_encoder_misr_read() local
2037 if (!phys || !phys->ops.collect_misr) in _dpu_encoder_misr_read()
2041 "Intf idx:%d\n", phys->intf_idx - INTF_0); in _dpu_encoder_misr_read()
2043 phys->ops.collect_misr(phys)); in _dpu_encoder_misr_read()
2296 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in dpu_encoder_setup_display() local
2298 if (phys) { in dpu_encoder_setup_display()
2299 atomic_set(&phys->vsync_cnt, 0); in dpu_encoder_setup_display()
2300 atomic_set(&phys->underrun_cnt, 0); in dpu_encoder_setup_display()
2446 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in dpu_encoder_wait_for_event() local
2447 if (!phys) in dpu_encoder_wait_for_event()
2452 fn_wait = phys->ops.wait_for_commit_done; in dpu_encoder_wait_for_event()
2455 fn_wait = phys->ops.wait_for_tx_complete; in dpu_encoder_wait_for_event()
2458 fn_wait = phys->ops.wait_for_vblank; in dpu_encoder_wait_for_event()
2468 ret = fn_wait(phys); in dpu_encoder_wait_for_event()
2493 struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; in dpu_encoder_get_intf_mode() local
2495 if (phys) in dpu_encoder_get_intf_mode()
2496 return phys->intf_mode; in dpu_encoder_get_intf_mode()