Lines Matching refs:gmu
14 struct a6xx_gmu *gmu = data; in a6xx_gmu_irq() local
17 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS); in a6xx_gmu_irq()
18 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status); in a6xx_gmu_irq()
21 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n"); in a6xx_gmu_irq()
28 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n"); in a6xx_gmu_irq()
31 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n", in a6xx_gmu_irq()
32 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS)); in a6xx_gmu_irq()
39 struct a6xx_gmu *gmu = data; in a6xx_hfi_irq() local
42 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO); in a6xx_hfi_irq()
43 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status); in a6xx_hfi_irq()
46 tasklet_schedule(&gmu->hfi_tasklet); in a6xx_hfi_irq()
49 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n"); in a6xx_hfi_irq()
59 static bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) in a6xx_gmu_gx_is_on() argument
61 u32 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); in a6xx_gmu_gx_is_on()
68 static int a6xx_gmu_set_freq(struct a6xx_gmu *gmu, int index) in a6xx_gmu_set_freq() argument
70 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0); in a6xx_gmu_set_freq()
72 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING, in a6xx_gmu_set_freq()
79 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff); in a6xx_gmu_set_freq()
82 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET); in a6xx_gmu_set_freq()
83 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET); in a6xx_gmu_set_freq()
85 return gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN); in a6xx_gmu_set_freq()
88 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu) in a6xx_gmu_check_idle_level() argument
91 int local = gmu->idle_level; in a6xx_gmu_check_idle_level()
94 if (gmu->idle_level == GMU_IDLE_STATE_SPTP) in a6xx_gmu_check_idle_level()
97 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); in a6xx_gmu_check_idle_level()
100 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || in a6xx_gmu_check_idle_level()
101 !a6xx_gmu_gx_is_on(gmu)) in a6xx_gmu_check_idle_level()
111 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_gmu_wait_for_idle() local
113 return spin_until(a6xx_gmu_check_idle_level(gmu)); in a6xx_gmu_wait_for_idle()
116 static int a6xx_gmu_start(struct a6xx_gmu *gmu) in a6xx_gmu_start() argument
121 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1); in a6xx_gmu_start()
122 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0); in a6xx_gmu_start()
124 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val, in a6xx_gmu_start()
128 dev_err(gmu->dev, "GMU firmware initialization timed out\n"); in a6xx_gmu_start()
133 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu) in a6xx_gmu_hfi_start() argument
138 gmu_rmw(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, in a6xx_gmu_hfi_start()
141 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1); in a6xx_gmu_hfi_start()
143 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val, in a6xx_gmu_hfi_start()
146 dev_err(gmu->dev, "Unable to start the HFI queues\n"); in a6xx_gmu_hfi_start()
152 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) in a6xx_gmu_set_oob() argument
180 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request); in a6xx_gmu_set_oob()
183 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, in a6xx_gmu_set_oob()
187 dev_err(gmu->dev, in a6xx_gmu_set_oob()
190 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO)); in a6xx_gmu_set_oob()
193 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack); in a6xx_gmu_set_oob()
199 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state) in a6xx_gmu_clear_oob() argument
203 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, in a6xx_gmu_clear_oob()
207 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, in a6xx_gmu_clear_oob()
211 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, in a6xx_gmu_clear_oob()
218 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu) in a6xx_sptprac_enable() argument
223 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000); in a6xx_sptprac_enable()
225 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, in a6xx_sptprac_enable()
229 dev_err(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n", in a6xx_sptprac_enable()
230 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); in a6xx_sptprac_enable()
237 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu) in a6xx_sptprac_disable() argument
243 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11)); in a6xx_sptprac_disable()
245 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001); in a6xx_sptprac_disable()
247 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val, in a6xx_sptprac_disable()
251 dev_err(gmu->dev, "failed to power off SPTPRAC: 0x%x\n", in a6xx_sptprac_disable()
252 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS)); in a6xx_sptprac_disable()
256 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu) in a6xx_gmu_gfx_rail_on() argument
261 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0); in a6xx_gmu_gfx_rail_on()
264 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1]; in a6xx_gmu_gfx_rail_on()
266 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff); in a6xx_gmu_gfx_rail_on()
267 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff); in a6xx_gmu_gfx_rail_on()
270 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); in a6xx_gmu_gfx_rail_on()
274 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu) in a6xx_gmu_notify_slumber() argument
279 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); in a6xx_gmu_notify_slumber()
282 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) in a6xx_gmu_notify_slumber()
283 a6xx_sptprac_disable(gmu); in a6xx_gmu_notify_slumber()
286 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1); in a6xx_gmu_notify_slumber()
288 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER); in a6xx_gmu_notify_slumber()
289 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); in a6xx_gmu_notify_slumber()
293 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE) in a6xx_gmu_notify_slumber()
295 dev_err(gmu->dev, "The GMU did not go into slumber\n"); in a6xx_gmu_notify_slumber()
301 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); in a6xx_gmu_notify_slumber()
305 static int a6xx_rpmh_start(struct a6xx_gmu *gmu) in a6xx_rpmh_start() argument
310 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1); in a6xx_rpmh_start()
314 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val, in a6xx_rpmh_start()
317 dev_err(gmu->dev, "Unable to power on the GPU RSC\n"); in a6xx_rpmh_start()
321 ret = gmu_poll_timeout(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val, in a6xx_rpmh_start()
325 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); in a6xx_rpmh_start()
328 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); in a6xx_rpmh_start()
332 dev_err(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n"); in a6xx_rpmh_start()
336 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu) in a6xx_rpmh_stop() argument
341 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1); in a6xx_rpmh_stop()
343 ret = gmu_poll_timeout(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, in a6xx_rpmh_stop()
346 dev_err(gmu->dev, "Unable to power off the GPU RSC\n"); in a6xx_rpmh_stop()
348 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0); in a6xx_rpmh_stop()
351 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) in a6xx_gmu_rpmh_init() argument
354 gmu_write(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); in a6xx_gmu_rpmh_init()
357 gmu_write(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); in a6xx_gmu_rpmh_init()
358 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); in a6xx_gmu_rpmh_init()
359 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); in a6xx_gmu_rpmh_init()
360 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0); in a6xx_gmu_rpmh_init()
361 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0); in a6xx_gmu_rpmh_init()
362 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000); in a6xx_gmu_rpmh_init()
363 gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0); in a6xx_gmu_rpmh_init()
364 gmu_write(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0); in a6xx_gmu_rpmh_init()
365 gmu_write(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); in a6xx_gmu_rpmh_init()
366 gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); in a6xx_gmu_rpmh_init()
367 gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); in a6xx_gmu_rpmh_init()
370 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); in a6xx_gmu_rpmh_init()
371 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); in a6xx_gmu_rpmh_init()
372 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); in a6xx_gmu_rpmh_init()
373 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); in a6xx_gmu_rpmh_init()
374 gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8); in a6xx_gmu_rpmh_init()
377 pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1); in a6xx_gmu_rpmh_init()
378 pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2); in a6xx_gmu_rpmh_init()
379 pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0); in a6xx_gmu_rpmh_init()
380 pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284); in a6xx_gmu_rpmh_init()
381 pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc); in a6xx_gmu_rpmh_init()
384 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); in a6xx_gmu_rpmh_init()
385 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); in a6xx_gmu_rpmh_init()
386 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0); in a6xx_gmu_rpmh_init()
387 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108); in a6xx_gmu_rpmh_init()
388 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010); in a6xx_gmu_rpmh_init()
389 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1); in a6xx_gmu_rpmh_init()
390 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108); in a6xx_gmu_rpmh_init()
391 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000); in a6xx_gmu_rpmh_init()
392 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0); in a6xx_gmu_rpmh_init()
393 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108); in a6xx_gmu_rpmh_init()
394 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080); in a6xx_gmu_rpmh_init()
395 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0); in a6xx_gmu_rpmh_init()
396 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); in a6xx_gmu_rpmh_init()
397 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); in a6xx_gmu_rpmh_init()
398 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0); in a6xx_gmu_rpmh_init()
399 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108); in a6xx_gmu_rpmh_init()
400 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010); in a6xx_gmu_rpmh_init()
401 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2); in a6xx_gmu_rpmh_init()
402 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108); in a6xx_gmu_rpmh_init()
403 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000); in a6xx_gmu_rpmh_init()
404 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3); in a6xx_gmu_rpmh_init()
405 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108); in a6xx_gmu_rpmh_init()
406 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080); in a6xx_gmu_rpmh_init()
407 pdc_write(gmu, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3); in a6xx_gmu_rpmh_init()
410 pdc_write(gmu, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0); in a6xx_gmu_rpmh_init()
411 pdc_write(gmu, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001); in a6xx_gmu_rpmh_init()
426 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu) in a6xx_gmu_power_config() argument
429 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1); in a6xx_gmu_power_config()
431 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400); in a6xx_gmu_power_config()
433 switch (gmu->idle_level) { in a6xx_gmu_power_config()
435 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST, in a6xx_gmu_power_config()
437 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, in a6xx_gmu_power_config()
442 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST, in a6xx_gmu_power_config()
444 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, in a6xx_gmu_power_config()
450 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0, in a6xx_gmu_power_config()
459 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) in a6xx_gmu_fw_start() argument
462 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_fw_start()
469 ret = a6xx_rpmh_start(gmu); in a6xx_gmu_fw_start()
479 dev_err(gmu->dev, in a6xx_gmu_fw_start()
485 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1); in a6xx_gmu_fw_start()
489 a6xx_gmu_rpmh_init(gmu); in a6xx_gmu_fw_start()
492 ret = a6xx_rpmh_start(gmu); in a6xx_gmu_fw_start()
500 gmu_write(gmu, REG_A6XX_GMU_CM3_ITCM_START + i, in a6xx_gmu_fw_start()
504 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0); in a6xx_gmu_fw_start()
505 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02); in a6xx_gmu_fw_start()
508 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi->iova); in a6xx_gmu_fw_start()
509 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1); in a6xx_gmu_fw_start()
511 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, in a6xx_gmu_fw_start()
519 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); in a6xx_gmu_fw_start()
522 a6xx_gmu_power_config(gmu); in a6xx_gmu_fw_start()
524 ret = a6xx_gmu_start(gmu); in a6xx_gmu_fw_start()
528 ret = a6xx_gmu_gfx_rail_on(gmu); in a6xx_gmu_fw_start()
533 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) { in a6xx_gmu_fw_start()
534 ret = a6xx_sptprac_enable(gmu); in a6xx_gmu_fw_start()
539 ret = a6xx_gmu_hfi_start(gmu); in a6xx_gmu_fw_start()
558 static void a6xx_gmu_irq_enable(struct a6xx_gmu *gmu) in a6xx_gmu_irq_enable() argument
560 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0); in a6xx_gmu_irq_enable()
561 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0); in a6xx_gmu_irq_enable()
563 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, in a6xx_gmu_irq_enable()
565 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, in a6xx_gmu_irq_enable()
568 enable_irq(gmu->gmu_irq); in a6xx_gmu_irq_enable()
569 enable_irq(gmu->hfi_irq); in a6xx_gmu_irq_enable()
572 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu) in a6xx_gmu_irq_disable() argument
574 disable_irq(gmu->gmu_irq); in a6xx_gmu_irq_disable()
575 disable_irq(gmu->hfi_irq); in a6xx_gmu_irq_disable()
577 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0); in a6xx_gmu_irq_disable()
578 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0); in a6xx_gmu_irq_disable()
583 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_gmu_reset() local
588 a6xx_hfi_stop(gmu); in a6xx_gmu_reset()
591 a6xx_gmu_irq_disable(gmu); in a6xx_gmu_reset()
594 a6xx_sptprac_disable(gmu); in a6xx_gmu_reset()
597 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val, in a6xx_gmu_reset()
599 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val, in a6xx_gmu_reset()
601 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val, in a6xx_gmu_reset()
603 gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val, in a6xx_gmu_reset()
607 regulator_force_disable(gmu->gx); in a6xx_gmu_reset()
610 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); in a6xx_gmu_reset()
611 pm_runtime_put_sync(gmu->dev); in a6xx_gmu_reset()
614 pm_runtime_get_sync(gmu->dev); in a6xx_gmu_reset()
617 clk_set_rate(gmu->core_clk, 200000000); in a6xx_gmu_reset()
618 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); in a6xx_gmu_reset()
622 a6xx_gmu_irq_enable(gmu); in a6xx_gmu_reset()
624 ret = a6xx_gmu_fw_start(gmu, GMU_RESET); in a6xx_gmu_reset()
626 ret = a6xx_hfi_start(gmu, GMU_COLD_BOOT); in a6xx_gmu_reset()
629 a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1); in a6xx_gmu_reset()
633 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); in a6xx_gmu_reset()
640 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_gmu_resume() local
643 if (WARN(!gmu->mmio, "The GMU is not set up yet\n")) in a6xx_gmu_resume()
647 pm_runtime_get_sync(gmu->dev); in a6xx_gmu_resume()
650 clk_set_rate(gmu->core_clk, 200000000); in a6xx_gmu_resume()
651 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks); in a6xx_gmu_resume()
655 a6xx_gmu_irq_enable(gmu); in a6xx_gmu_resume()
658 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ? in a6xx_gmu_resume()
661 ret = a6xx_gmu_fw_start(gmu, status); in a6xx_gmu_resume()
665 ret = a6xx_hfi_start(gmu, status); in a6xx_gmu_resume()
668 a6xx_gmu_set_freq(gmu, gmu->nr_gpu_freqs - 1); in a6xx_gmu_resume()
673 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER); in a6xx_gmu_resume()
678 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu) in a6xx_gmu_isidle() argument
682 if (!gmu->mmio) in a6xx_gmu_isidle()
685 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS); in a6xx_gmu_isidle()
695 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_gmu_stop() local
702 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE); in a6xx_gmu_stop()
711 a6xx_gmu_notify_slumber(gmu); in a6xx_gmu_stop()
713 ret = gmu_poll_timeout(gmu, in a6xx_gmu_stop()
724 dev_err(gmu->dev, in a6xx_gmu_stop()
726 gmu_read(gmu, in a6xx_gmu_stop()
728 gmu_read(gmu, in a6xx_gmu_stop()
733 a6xx_hfi_stop(gmu); in a6xx_gmu_stop()
736 a6xx_gmu_irq_disable(gmu); in a6xx_gmu_stop()
739 a6xx_rpmh_stop(gmu); in a6xx_gmu_stop()
741 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); in a6xx_gmu_stop()
743 pm_runtime_put_sync(gmu->dev); in a6xx_gmu_stop()
748 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo) in a6xx_gmu_memory_free() argument
760 iommu_unmap(gmu->domain, iova, PAGE_SIZE); in a6xx_gmu_memory_free()
768 static struct a6xx_gmu_bo *a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, in a6xx_gmu_memory_alloc() argument
794 bo->iova = gmu->uncached_iova_base; in a6xx_gmu_memory_alloc()
797 ret = iommu_map(gmu->domain, in a6xx_gmu_memory_alloc()
803 dev_err(gmu->dev, "Unable to map GMU buffer object\n"); in a6xx_gmu_memory_alloc()
806 iommu_unmap(gmu->domain, in a6xx_gmu_memory_alloc()
820 gmu->uncached_iova_base += ALIGN(size, SZ_1M); in a6xx_gmu_memory_alloc()
836 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu) in a6xx_gmu_memory_probe() argument
845 gmu->uncached_iova_base = 0x60000000; in a6xx_gmu_memory_probe()
848 gmu->domain = iommu_domain_alloc(&platform_bus_type); in a6xx_gmu_memory_probe()
849 if (!gmu->domain) in a6xx_gmu_memory_probe()
852 ret = iommu_attach_device(gmu->domain, gmu->dev); in a6xx_gmu_memory_probe()
855 iommu_domain_free(gmu->domain); in a6xx_gmu_memory_probe()
856 gmu->domain = NULL; in a6xx_gmu_memory_probe()
967 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu) in a6xx_gmu_rpmh_votes_init() argument
969 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_rpmh_votes_init()
983 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes, in a6xx_gmu_rpmh_votes_init()
984 gmu->gpu_freqs, gmu->nr_gpu_freqs, in a6xx_gmu_rpmh_votes_init()
988 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes, in a6xx_gmu_rpmh_votes_init()
989 gmu->gmu_freqs, gmu->nr_gmu_freqs, in a6xx_gmu_rpmh_votes_init()
1027 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu) in a6xx_gmu_pwrlevels_probe() argument
1029 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_gmu_pwrlevels_probe()
1039 ret = dev_pm_opp_of_add_table(gmu->dev); in a6xx_gmu_pwrlevels_probe()
1041 dev_err(gmu->dev, "Unable to set the OPP table for the GMU\n"); in a6xx_gmu_pwrlevels_probe()
1045 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev, in a6xx_gmu_pwrlevels_probe()
1046 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs)); in a6xx_gmu_pwrlevels_probe()
1052 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev, in a6xx_gmu_pwrlevels_probe()
1053 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs)); in a6xx_gmu_pwrlevels_probe()
1056 return a6xx_gmu_rpmh_votes_init(gmu); in a6xx_gmu_pwrlevels_probe()
1059 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu) in a6xx_gmu_clocks_probe() argument
1061 int ret = msm_clk_bulk_get(gmu->dev, &gmu->clocks); in a6xx_gmu_clocks_probe()
1066 gmu->nr_clocks = ret; in a6xx_gmu_clocks_probe()
1068 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks, in a6xx_gmu_clocks_probe()
1069 gmu->nr_clocks, "gmu"); in a6xx_gmu_clocks_probe()
1095 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, in a6xx_gmu_get_irq() argument
1103 name, gmu); in a6xx_gmu_get_irq()
1116 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_gmu_remove() local
1118 if (IS_ERR_OR_NULL(gmu->mmio)) in a6xx_gmu_remove()
1121 pm_runtime_disable(gmu->dev); in a6xx_gmu_remove()
1124 a6xx_gmu_irq_disable(gmu); in a6xx_gmu_remove()
1125 a6xx_gmu_memory_free(gmu, gmu->hfi); in a6xx_gmu_remove()
1127 iommu_detach_device(gmu->domain, gmu->dev); in a6xx_gmu_remove()
1129 iommu_domain_free(gmu->domain); in a6xx_gmu_remove()
1134 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_gmu_probe() local
1141 gmu->dev = &pdev->dev; in a6xx_gmu_probe()
1143 of_dma_configure(gmu->dev, node, false); in a6xx_gmu_probe()
1146 gmu->idle_level = GMU_IDLE_STATE_ACTIVE; in a6xx_gmu_probe()
1148 pm_runtime_enable(gmu->dev); in a6xx_gmu_probe()
1149 gmu->gx = devm_regulator_get(gmu->dev, "vdd"); in a6xx_gmu_probe()
1152 ret = a6xx_gmu_clocks_probe(gmu); in a6xx_gmu_probe()
1157 ret = a6xx_gmu_memory_probe(gmu); in a6xx_gmu_probe()
1162 gmu->hfi = a6xx_gmu_memory_alloc(gmu, SZ_16K); in a6xx_gmu_probe()
1163 if (IS_ERR(gmu->hfi)) in a6xx_gmu_probe()
1167 gmu->debug = a6xx_gmu_memory_alloc(gmu, SZ_16K); in a6xx_gmu_probe()
1168 if (IS_ERR(gmu->debug)) in a6xx_gmu_probe()
1172 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu"); in a6xx_gmu_probe()
1175 gmu->pdc_mmio = a6xx_gmu_get_mmio(pdev, "gmu_pdc"); in a6xx_gmu_probe()
1177 if (IS_ERR(gmu->mmio) || IS_ERR(gmu->pdc_mmio)) in a6xx_gmu_probe()
1181 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq); in a6xx_gmu_probe()
1182 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq); in a6xx_gmu_probe()
1184 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) in a6xx_gmu_probe()
1188 tasklet_init(&gmu->hfi_tasklet, a6xx_hfi_task, (unsigned long) gmu); in a6xx_gmu_probe()
1191 a6xx_gmu_pwrlevels_probe(gmu); in a6xx_gmu_probe()
1194 a6xx_hfi_init(gmu); in a6xx_gmu_probe()
1198 a6xx_gmu_memory_free(gmu, gmu->hfi); in a6xx_gmu_probe()
1200 if (gmu->domain) { in a6xx_gmu_probe()
1201 iommu_detach_device(gmu->domain, gmu->dev); in a6xx_gmu_probe()
1203 iommu_domain_free(gmu->domain); in a6xx_gmu_probe()