64 	writel_relaxed(BIT(3) /* Enable scaler */ |  in meson_vpp_setup_interlace_vscaler_osd1()
68 	writel_relaxed(((drm_rect_width(input) - 1) << 16) |  in meson_vpp_setup_interlace_vscaler_osd1()
72 	writel_relaxed(((input->x1) << 16) | (input->x2),  in meson_vpp_setup_interlace_vscaler_osd1()
74 	writel_relaxed(((input->y1 >> 1) << 16) | (input->y2 >> 1),  in meson_vpp_setup_interlace_vscaler_osd1()
78 	writel_relaxed(BIT(16), priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE));  in meson_vpp_setup_interlace_vscaler_osd1()
79 	writel_relaxed(BIT(25), priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP));  in meson_vpp_setup_interlace_vscaler_osd1()
81 	writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));  in meson_vpp_setup_interlace_vscaler_osd1()
83 	writel_relaxed((4 << 0) /* osd_vsc_bank_length */ |  in meson_vpp_setup_interlace_vscaler_osd1()
95 	writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));  in meson_vpp_disable_interlace_vscaler_osd1()
96 	writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));  in meson_vpp_disable_interlace_vscaler_osd1()
97 	writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));  in meson_vpp_disable_interlace_vscaler_osd1()
118 	writel_relaxed(is_horizontal ? BIT(8) : 0,  in meson_vpp_write_scaling_filter_coefs()
121 		writel_relaxed(coefs[i],  in meson_vpp_write_scaling_filter_coefs()
129 		writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));  in meson_vpp_init()
133 		writel_relaxed(0x20000, priv->io_base + _REG(VPP_DOLBY_CTRL));  in meson_vpp_init()
134 		writel_relaxed(0x1020080,  in meson_vpp_init()
139 	writel_relaxed(readl_relaxed(priv->io_base + _REG(VPP_OFIFO_SIZE)) |  in meson_vpp_init()
141 	writel_relaxed(0x08080808, priv->io_base + _REG(VPP_HOLD_LINES));  in meson_vpp_init()
157 	writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));  in meson_vpp_init()
158 	writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));  in meson_vpp_init()
159 	writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));  in meson_vpp_init()