Lines Matching refs:regmap_update_bits
145 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0); in meson_vid_pll_set()
146 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0); in meson_vid_pll_set()
209 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
213 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
216 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
218 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
220 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
224 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
226 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
228 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
231 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
236 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, in meson_vid_pll_set()
268 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
270 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
279 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0); in meson_venci_cvbs_clock_config()
285 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
289 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
292 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN); in meson_venci_cvbs_clock_config()
295 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_venci_cvbs_clock_config()
298 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
302 regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV, in meson_venci_cvbs_clock_config()
306 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
310 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
312 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, in meson_venci_cvbs_clock_config()
316 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_venci_cvbs_clock_config()
319 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_venci_cvbs_clock_config()
444 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
460 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
462 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_hdmi_pll_set_params()
471 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
475 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
479 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
483 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
487 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
491 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3, in meson_hdmi_pll_set_params()
636 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
638 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
640 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
683 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
685 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
692 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
696 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
701 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
705 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
710 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
714 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
719 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
723 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
728 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
732 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL, in meson_vclk_set()
736 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_vclk_set()
743 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
748 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
752 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
757 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
762 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
766 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
771 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
776 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
780 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
785 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
790 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
794 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
799 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, in meson_vclk_set()
804 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
808 regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV, in meson_vclk_set()
815 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_vclk_set()
819 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2, in meson_vclk_set()
822 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN); in meson_vclk_set()