202 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)  in mtk_dsi_mask()  function
233 	mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);  in mtk_dsi_enable()
238 	mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);  in mtk_dsi_disable()
243 	mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);  in mtk_dsi_reset_engine()
244 	mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);  in mtk_dsi_reset_engine()
249 	mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);  in mtk_dsi_clk_ulp_mode_enter()
250 	mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);  in mtk_dsi_clk_ulp_mode_enter()
255 	mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);  in mtk_dsi_clk_ulp_mode_leave()
256 	mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);  in mtk_dsi_clk_ulp_mode_leave()
257 	mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);  in mtk_dsi_clk_ulp_mode_leave()
262 	mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);  in mtk_dsi_lane0_ulp_mode_enter()
263 	mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);  in mtk_dsi_lane0_ulp_mode_enter()
268 	mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);  in mtk_dsi_lane0_ulp_mode_leave()
269 	mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);  in mtk_dsi_lane0_ulp_mode_leave()
270 	mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);  in mtk_dsi_lane0_ulp_mode_leave()
284 		mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);  in mtk_dsi_clk_hs_mode()
286 		mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);  in mtk_dsi_clk_hs_mode()
307 	mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);  in mtk_dsi_set_vm_cmd()
308 	mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);  in mtk_dsi_set_vm_cmd()
504 			mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);  in mtk_dsi_irq()
508 		mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);  in mtk_dsi_irq()
955 	mtk_dsi_mask(dsi, DSI_CMDQ0, cmdq_mask, reg_val);  in mtk_dsi_cmdq()
956 	mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);  in mtk_dsi_cmdq()