Lines Matching refs:dsi_pll
102 config->dsi_pll.ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); in dsi_calc_mnp()
103 config->dsi_pll.div = in dsi_calc_mnp()
132 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI0_DSIPLL; in vlv_dsi_pll_compute()
135 config->dsi_pll.ctrl |= DSI_PLL_CLK_GATE_DSI1_DSIPLL; in vlv_dsi_pll_compute()
137 config->dsi_pll.ctrl |= DSI_PLL_VCO_EN; in vlv_dsi_pll_compute()
140 config->dsi_pll.div, config->dsi_pll.ctrl); in vlv_dsi_pll_compute()
155 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div); in vlv_dsi_pll_enable()
157 config->dsi_pll.ctrl & ~DSI_PLL_VCO_EN); in vlv_dsi_pll_enable()
164 vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, config->dsi_pll.ctrl); in vlv_dsi_pll_enable()
282 config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK; in vlv_dsi_get_pclk()
283 config->dsi_pll.div = pll_div; in vlv_dsi_get_pclk()
345 config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL); in bxt_dsi_get_pclk()
347 dsi_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; in bxt_dsi_get_pclk()
385 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; in glk_dsi_program_esc_clock()
442 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; in bxt_dsi_program_clocks()
511 config->dsi_pll.ctrl = dsi_ratio | BXT_DSIA_16X_BY2 | BXT_DSIC_16X_BY2; in bxt_dsi_pll_compute()
517 config->dsi_pll.ctrl |= BXT_DSI_PLL_PVD_RATIO_1; in bxt_dsi_pll_compute()
533 I915_WRITE(BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); in bxt_dsi_pll_enable()