Lines Matching refs:MIPI_CTRL

373 		tmp = I915_READ(MIPI_CTRL(port));  in glk_dsi_enable_io()
374 I915_WRITE(MIPI_CTRL(port), tmp | GLK_MIPIIO_ENABLE); in glk_dsi_enable_io()
378 tmp = I915_READ(MIPI_CTRL(PORT_A)); in glk_dsi_enable_io()
380 I915_WRITE(MIPI_CTRL(PORT_A), tmp); in glk_dsi_enable_io()
384 tmp = I915_READ(MIPI_CTRL(port)); in glk_dsi_enable_io()
389 I915_WRITE(MIPI_CTRL(port), tmp); in glk_dsi_enable_io()
395 MIPI_CTRL(port), GLK_MIPIIO_PORT_POWERED, in glk_dsi_enable_io()
419 MIPI_CTRL(port), GLK_PHY_STATUS_PORT_READY, in glk_dsi_device_ready()
425 val = I915_READ(MIPI_CTRL(PORT_A)); in glk_dsi_device_ready()
426 I915_WRITE(MIPI_CTRL(PORT_A), val | GLK_MIPIIO_RESET_RELEASED); in glk_dsi_device_ready()
445 MIPI_CTRL(port), GLK_ULPS_NOT_ACTIVE, 0, 20)) in glk_dsi_device_ready()
460 val = I915_READ(MIPI_CTRL(port)); in glk_dsi_device_ready()
462 I915_WRITE(MIPI_CTRL(port), val); in glk_dsi_device_ready()
469 MIPI_CTRL(port), GLK_DATA_LANE_STOP_STATE, in glk_dsi_device_ready()
579 MIPI_CTRL(port), in glk_dsi_enter_low_power_mode()
587 MIPI_CTRL(port), in glk_dsi_enter_low_power_mode()
601 tmp = I915_READ(MIPI_CTRL(PORT_A)); in glk_dsi_disable_mipi_io()
603 I915_WRITE(MIPI_CTRL(PORT_A), tmp); in glk_dsi_disable_mipi_io()
608 MIPI_CTRL(port), in glk_dsi_disable_mipi_io()
615 tmp = I915_READ(MIPI_CTRL(port)); in glk_dsi_disable_mipi_io()
617 I915_WRITE(MIPI_CTRL(port), tmp); in glk_dsi_disable_mipi_io()
684 temp = I915_READ(MIPI_CTRL(port)); in intel_dsi_port_enable()
688 I915_WRITE(MIPI_CTRL(port), temp); in intel_dsi_port_enable()
1068 u32 tmp = I915_READ(MIPI_CTRL(port)); in intel_dsi_get_hw_state()
1430 tmp = I915_READ(MIPI_CTRL(PORT_A)); in intel_dsi_prepare()
1432 I915_WRITE(MIPI_CTRL(PORT_A), tmp | in intel_dsi_prepare()
1436 tmp = I915_READ(MIPI_CTRL(port)); in intel_dsi_prepare()
1438 I915_WRITE(MIPI_CTRL(port), tmp | in intel_dsi_prepare()
1443 tmp = I915_READ(MIPI_CTRL(port)); in intel_dsi_prepare()
1447 I915_WRITE(MIPI_CTRL(port), tmp); in intel_dsi_prepare()