Lines Matching refs:dev_priv
52 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
56 lookup_power_well(struct drm_i915_private *dev_priv,
159 static void intel_power_well_enable(struct drm_i915_private *dev_priv, in intel_power_well_enable() argument
163 power_well->ops->enable(dev_priv, power_well); in intel_power_well_enable()
167 static void intel_power_well_disable(struct drm_i915_private *dev_priv, in intel_power_well_disable() argument
172 power_well->ops->disable(dev_priv, power_well); in intel_power_well_disable()
175 static void intel_power_well_get(struct drm_i915_private *dev_priv, in intel_power_well_get() argument
179 intel_power_well_enable(dev_priv, power_well); in intel_power_well_get()
182 static void intel_power_well_put(struct drm_i915_private *dev_priv, in intel_power_well_put() argument
189 intel_power_well_disable(dev_priv, power_well); in intel_power_well_put()
204 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, in __intel_display_power_is_enabled() argument
210 if (dev_priv->runtime_pm.suspended) in __intel_display_power_is_enabled()
215 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) { in __intel_display_power_is_enabled()
245 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, in intel_display_power_is_enabled() argument
251 power_domains = &dev_priv->power_domains; in intel_display_power_is_enabled()
254 ret = __intel_display_power_is_enabled(dev_priv, domain); in intel_display_power_is_enabled()
270 void intel_display_set_init_power(struct drm_i915_private *dev_priv, in intel_display_set_init_power() argument
273 if (dev_priv->power_domains.init_power_on == enable) in intel_display_set_init_power()
277 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); in intel_display_set_init_power()
279 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); in intel_display_set_init_power()
281 dev_priv->power_domains.init_power_on = enable; in intel_display_set_init_power()
290 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv, in hsw_power_well_post_enable() argument
293 struct pci_dev *pdev = dev_priv->drm.pdev; in hsw_power_well_post_enable()
312 gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask); in hsw_power_well_post_enable()
315 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv, in hsw_power_well_pre_disable() argument
319 gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask); in hsw_power_well_pre_disable()
323 static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv, in hsw_wait_for_power_well_enable() argument
329 WARN_ON(intel_wait_for_register(dev_priv, in hsw_wait_for_power_well_enable()
336 static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv, in hsw_power_well_requesters() argument
350 static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv, in hsw_wait_for_power_well_disable() argument
368 (reqs = hsw_power_well_requesters(dev_priv, id)), 1); in hsw_wait_for_power_well_disable()
377 static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv, in gen9_wait_for_power_well_fuses() argument
381 WARN_ON(intel_wait_for_register(dev_priv, SKL_FUSE_STATUS, in gen9_wait_for_power_well_fuses()
386 static void hsw_power_well_enable(struct drm_i915_private *dev_priv, in hsw_power_well_enable() argument
395 pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_TO_PG(id) : in hsw_power_well_enable()
405 gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0); in hsw_power_well_enable()
410 hsw_wait_for_power_well_enable(dev_priv, power_well); in hsw_power_well_enable()
413 if (IS_CANNONLAKE(dev_priv) && in hsw_power_well_enable()
422 gen9_wait_for_power_well_fuses(dev_priv, pg); in hsw_power_well_enable()
424 hsw_power_well_post_enable(dev_priv, power_well->hsw.irq_pipe_mask, in hsw_power_well_enable()
428 static void hsw_power_well_disable(struct drm_i915_private *dev_priv, in hsw_power_well_disable() argument
434 hsw_power_well_pre_disable(dev_priv, power_well->hsw.irq_pipe_mask); in hsw_power_well_disable()
439 hsw_wait_for_power_well_disable(dev_priv, power_well); in hsw_power_well_disable()
445 icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv, in icl_combo_phy_aux_power_well_enable() argument
458 hsw_wait_for_power_well_enable(dev_priv, power_well); in icl_combo_phy_aux_power_well_enable()
462 icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv, in icl_combo_phy_aux_power_well_disable() argument
476 hsw_wait_for_power_well_disable(dev_priv, power_well); in icl_combo_phy_aux_power_well_disable()
484 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, in hsw_power_well_enabled() argument
493 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) in assert_can_enable_dc9() argument
504 WARN_ONCE(intel_irqs_enabled(dev_priv), in assert_can_enable_dc9()
516 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) in assert_can_disable_dc9() argument
518 WARN_ONCE(intel_irqs_enabled(dev_priv), in assert_can_disable_dc9()
532 static void gen9_write_dc_state(struct drm_i915_private *dev_priv, in gen9_write_dc_state() argument
569 static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) in gen9_dc_mask() argument
574 if (IS_GEN9_LP(dev_priv)) in gen9_dc_mask()
582 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) in gen9_sanitize_dc_state() argument
586 val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); in gen9_sanitize_dc_state()
589 dev_priv->csr.dc_state, val); in gen9_sanitize_dc_state()
590 dev_priv->csr.dc_state = val; in gen9_sanitize_dc_state()
616 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) in gen9_set_dc_state() argument
621 if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) in gen9_set_dc_state()
622 state &= dev_priv->csr.allowed_dc_mask; in gen9_set_dc_state()
625 mask = gen9_dc_mask(dev_priv); in gen9_set_dc_state()
630 if ((val & mask) != dev_priv->csr.dc_state) in gen9_set_dc_state()
632 dev_priv->csr.dc_state, val & mask); in gen9_set_dc_state()
637 gen9_write_dc_state(dev_priv, val); in gen9_set_dc_state()
639 dev_priv->csr.dc_state = val & mask; in gen9_set_dc_state()
642 void bxt_enable_dc9(struct drm_i915_private *dev_priv) in bxt_enable_dc9() argument
644 assert_can_enable_dc9(dev_priv); in bxt_enable_dc9()
648 intel_power_sequencer_reset(dev_priv); in bxt_enable_dc9()
649 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); in bxt_enable_dc9()
652 void bxt_disable_dc9(struct drm_i915_private *dev_priv) in bxt_disable_dc9() argument
654 assert_can_disable_dc9(dev_priv); in bxt_disable_dc9()
658 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in bxt_disable_dc9()
660 intel_pps_unlock_regs_wa(dev_priv); in bxt_disable_dc9()
663 static void assert_csr_loaded(struct drm_i915_private *dev_priv) in assert_csr_loaded() argument
671 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) in assert_can_enable_dc5() argument
673 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, in assert_can_enable_dc5()
680 assert_rpm_wakelock_held(dev_priv); in assert_can_enable_dc5()
682 assert_csr_loaded(dev_priv); in assert_can_enable_dc5()
685 void gen9_enable_dc5(struct drm_i915_private *dev_priv) in gen9_enable_dc5() argument
687 assert_can_enable_dc5(dev_priv); in gen9_enable_dc5()
692 if (IS_GEN9_BC(dev_priv)) in gen9_enable_dc5()
696 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); in gen9_enable_dc5()
699 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) in assert_can_enable_dc6() argument
706 assert_csr_loaded(dev_priv); in assert_can_enable_dc6()
709 static void skl_enable_dc6(struct drm_i915_private *dev_priv) in skl_enable_dc6() argument
711 assert_can_enable_dc6(dev_priv); in skl_enable_dc6()
716 if (IS_GEN9_BC(dev_priv)) in skl_enable_dc6()
720 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); in skl_enable_dc6()
723 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, in hsw_power_well_sync_hw() argument
740 static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, in bxt_dpio_cmn_power_well_enable() argument
743 bxt_ddi_phy_init(dev_priv, power_well->bxt.phy); in bxt_dpio_cmn_power_well_enable()
746 static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, in bxt_dpio_cmn_power_well_disable() argument
749 bxt_ddi_phy_uninit(dev_priv, power_well->bxt.phy); in bxt_dpio_cmn_power_well_disable()
752 static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv, in bxt_dpio_cmn_power_well_enabled() argument
755 return bxt_ddi_phy_is_enabled(dev_priv, power_well->bxt.phy); in bxt_dpio_cmn_power_well_enabled()
758 static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv) in bxt_verify_ddi_phy_power_wells() argument
762 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A); in bxt_verify_ddi_phy_power_wells()
764 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); in bxt_verify_ddi_phy_power_wells()
766 power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_BC); in bxt_verify_ddi_phy_power_wells()
768 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); in bxt_verify_ddi_phy_power_wells()
770 if (IS_GEMINILAKE(dev_priv)) { in bxt_verify_ddi_phy_power_wells()
771 power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C); in bxt_verify_ddi_phy_power_wells()
773 bxt_ddi_phy_verify_state(dev_priv, power_well->bxt.phy); in bxt_verify_ddi_phy_power_wells()
777 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, in gen9_dc_off_power_well_enabled() argument
783 static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv) in gen9_assert_dbuf_enabled() argument
792 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, in gen9_dc_off_power_well_enable() argument
797 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in gen9_dc_off_power_well_enable()
799 dev_priv->display.get_cdclk(dev_priv, &cdclk_state); in gen9_dc_off_power_well_enable()
801 WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state)); in gen9_dc_off_power_well_enable()
803 gen9_assert_dbuf_enabled(dev_priv); in gen9_dc_off_power_well_enable()
805 if (IS_GEN9_LP(dev_priv)) in gen9_dc_off_power_well_enable()
806 bxt_verify_ddi_phy_power_wells(dev_priv); in gen9_dc_off_power_well_enable()
809 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, in gen9_dc_off_power_well_disable() argument
812 if (!dev_priv->csr.dmc_payload) in gen9_dc_off_power_well_disable()
815 if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) in gen9_dc_off_power_well_disable()
816 skl_enable_dc6(dev_priv); in gen9_dc_off_power_well_disable()
817 else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) in gen9_dc_off_power_well_disable()
818 gen9_enable_dc5(dev_priv); in gen9_dc_off_power_well_disable()
821 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv, in i9xx_power_well_sync_hw_noop() argument
826 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, in i9xx_always_on_power_well_noop() argument
831 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, in i9xx_always_on_power_well_enabled() argument
837 static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, in i830_pipes_power_well_enable() argument
841 i830_enable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_enable()
843 i830_enable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_enable()
846 static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, in i830_pipes_power_well_disable() argument
849 i830_disable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_disable()
850 i830_disable_pipe(dev_priv, PIPE_A); in i830_pipes_power_well_disable()
853 static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, in i830_pipes_power_well_enabled() argument
860 static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, in i830_pipes_power_well_sync_hw() argument
864 i830_pipes_power_well_enable(dev_priv, power_well); in i830_pipes_power_well_sync_hw()
866 i830_pipes_power_well_disable(dev_priv, power_well); in i830_pipes_power_well_sync_hw()
869 static void vlv_set_power_well(struct drm_i915_private *dev_priv, in vlv_set_power_well() argument
881 mutex_lock(&dev_priv->pcu_lock); in vlv_set_power_well()
884 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) in vlv_set_power_well()
889 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); in vlv_set_power_well()
892 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); in vlv_set_power_well()
897 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); in vlv_set_power_well()
902 mutex_unlock(&dev_priv->pcu_lock); in vlv_set_power_well()
905 static void vlv_power_well_enable(struct drm_i915_private *dev_priv, in vlv_power_well_enable() argument
908 vlv_set_power_well(dev_priv, power_well, true); in vlv_power_well_enable()
911 static void vlv_power_well_disable(struct drm_i915_private *dev_priv, in vlv_power_well_disable() argument
914 vlv_set_power_well(dev_priv, power_well, false); in vlv_power_well_disable()
917 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, in vlv_power_well_enabled() argument
929 mutex_lock(&dev_priv->pcu_lock); in vlv_power_well_enabled()
931 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; in vlv_power_well_enabled()
945 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; in vlv_power_well_enabled()
948 mutex_unlock(&dev_priv->pcu_lock); in vlv_power_well_enabled()
953 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) in vlv_init_display_clock_gating() argument
974 WARN_ON(dev_priv->rawclk_freq == 0); in vlv_init_display_clock_gating()
977 DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000)); in vlv_init_display_clock_gating()
980 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) in vlv_display_power_well_init() argument
993 for_each_pipe(dev_priv, pipe) { in vlv_display_power_well_init()
1003 vlv_init_display_clock_gating(dev_priv); in vlv_display_power_well_init()
1005 spin_lock_irq(&dev_priv->irq_lock); in vlv_display_power_well_init()
1006 valleyview_enable_display_irqs(dev_priv); in vlv_display_power_well_init()
1007 spin_unlock_irq(&dev_priv->irq_lock); in vlv_display_power_well_init()
1013 if (dev_priv->power_domains.initializing) in vlv_display_power_well_init()
1016 intel_hpd_init(dev_priv); in vlv_display_power_well_init()
1019 for_each_intel_encoder(&dev_priv->drm, encoder) { in vlv_display_power_well_init()
1024 i915_redisable_vga_power_on(dev_priv); in vlv_display_power_well_init()
1026 intel_pps_unlock_regs_wa(dev_priv); in vlv_display_power_well_init()
1029 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) in vlv_display_power_well_deinit() argument
1031 spin_lock_irq(&dev_priv->irq_lock); in vlv_display_power_well_deinit()
1032 valleyview_disable_display_irqs(dev_priv); in vlv_display_power_well_deinit()
1033 spin_unlock_irq(&dev_priv->irq_lock); in vlv_display_power_well_deinit()
1036 synchronize_irq(dev_priv->drm.irq); in vlv_display_power_well_deinit()
1038 intel_power_sequencer_reset(dev_priv); in vlv_display_power_well_deinit()
1041 if (!dev_priv->drm.dev->power.is_suspended) in vlv_display_power_well_deinit()
1042 intel_hpd_poll_init(dev_priv); in vlv_display_power_well_deinit()
1045 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, in vlv_display_power_well_enable() argument
1050 vlv_set_power_well(dev_priv, power_well, true); in vlv_display_power_well_enable()
1052 vlv_display_power_well_init(dev_priv); in vlv_display_power_well_enable()
1055 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, in vlv_display_power_well_disable() argument
1060 vlv_display_power_well_deinit(dev_priv); in vlv_display_power_well_disable()
1062 vlv_set_power_well(dev_priv, power_well, false); in vlv_display_power_well_disable()
1065 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, in vlv_dpio_cmn_power_well_enable() argument
1073 vlv_set_power_well(dev_priv, power_well, true); in vlv_dpio_cmn_power_well_enable()
1089 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, in vlv_dpio_cmn_power_well_disable() argument
1096 for_each_pipe(dev_priv, pipe) in vlv_dpio_cmn_power_well_disable()
1097 assert_pll_disabled(dev_priv, pipe); in vlv_dpio_cmn_power_well_disable()
1102 vlv_set_power_well(dev_priv, power_well, false); in vlv_dpio_cmn_power_well_disable()
1108 lookup_power_well(struct drm_i915_private *dev_priv, in lookup_power_well() argument
1111 struct i915_power_domains *power_domains = &dev_priv->power_domains; in lookup_power_well()
1127 static void assert_chv_phy_status(struct drm_i915_private *dev_priv) in assert_chv_phy_status() argument
1130 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); in assert_chv_phy_status()
1132 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); in assert_chv_phy_status()
1133 u32 phy_control = dev_priv->chv_phy_control; in assert_chv_phy_status()
1144 if (!dev_priv->chv_phy_assert[DPIO_PHY0]) in assert_chv_phy_status()
1152 if (!dev_priv->chv_phy_assert[DPIO_PHY1]) in assert_chv_phy_status()
1157 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { in assert_chv_phy_status()
1198 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { in assert_chv_phy_status()
1223 if (intel_wait_for_register(dev_priv, in assert_chv_phy_status()
1230 phy_status, dev_priv->chv_phy_control); in assert_chv_phy_status()
1235 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, in chv_dpio_cmn_power_well_enable() argument
1255 vlv_set_power_well(dev_priv, power_well, true); in chv_dpio_cmn_power_well_enable()
1258 if (intel_wait_for_register(dev_priv, in chv_dpio_cmn_power_well_enable()
1265 mutex_lock(&dev_priv->sb_lock); in chv_dpio_cmn_power_well_enable()
1268 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); in chv_dpio_cmn_power_well_enable()
1271 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); in chv_dpio_cmn_power_well_enable()
1274 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); in chv_dpio_cmn_power_well_enable()
1276 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); in chv_dpio_cmn_power_well_enable()
1283 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); in chv_dpio_cmn_power_well_enable()
1285 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); in chv_dpio_cmn_power_well_enable()
1288 mutex_unlock(&dev_priv->sb_lock); in chv_dpio_cmn_power_well_enable()
1290 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); in chv_dpio_cmn_power_well_enable()
1291 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); in chv_dpio_cmn_power_well_enable()
1294 phy, dev_priv->chv_phy_control); in chv_dpio_cmn_power_well_enable()
1296 assert_chv_phy_status(dev_priv); in chv_dpio_cmn_power_well_enable()
1299 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, in chv_dpio_cmn_power_well_disable() argument
1309 assert_pll_disabled(dev_priv, PIPE_A); in chv_dpio_cmn_power_well_disable()
1310 assert_pll_disabled(dev_priv, PIPE_B); in chv_dpio_cmn_power_well_disable()
1313 assert_pll_disabled(dev_priv, PIPE_C); in chv_dpio_cmn_power_well_disable()
1316 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); in chv_dpio_cmn_power_well_disable()
1317 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); in chv_dpio_cmn_power_well_disable()
1319 vlv_set_power_well(dev_priv, power_well, false); in chv_dpio_cmn_power_well_disable()
1322 phy, dev_priv->chv_phy_control); in chv_dpio_cmn_power_well_disable()
1325 dev_priv->chv_phy_assert[phy] = true; in chv_dpio_cmn_power_well_disable()
1327 assert_chv_phy_status(dev_priv); in chv_dpio_cmn_power_well_disable()
1330 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, in assert_chv_phy_powergate() argument
1343 if (!dev_priv->chv_phy_assert[phy]) in assert_chv_phy_powergate()
1351 mutex_lock(&dev_priv->sb_lock); in assert_chv_phy_powergate()
1352 val = vlv_dpio_read(dev_priv, pipe, reg); in assert_chv_phy_powergate()
1353 mutex_unlock(&dev_priv->sb_lock); in assert_chv_phy_powergate()
1392 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, in chv_phy_powergate_ch() argument
1395 struct i915_power_domains *power_domains = &dev_priv->power_domains; in chv_phy_powergate_ch()
1400 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_ch()
1406 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_ch()
1408 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_ch()
1410 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); in chv_phy_powergate_ch()
1413 phy, ch, dev_priv->chv_phy_control); in chv_phy_powergate_ch()
1415 assert_chv_phy_status(dev_priv); in chv_phy_powergate_ch()
1426 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in chv_phy_powergate_lanes() local
1427 struct i915_power_domains *power_domains = &dev_priv->power_domains; in chv_phy_powergate_lanes()
1433 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); in chv_phy_powergate_lanes()
1434 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); in chv_phy_powergate_lanes()
1437 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_lanes()
1439 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); in chv_phy_powergate_lanes()
1441 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); in chv_phy_powergate_lanes()
1444 phy, ch, mask, dev_priv->chv_phy_control); in chv_phy_powergate_lanes()
1446 assert_chv_phy_status(dev_priv); in chv_phy_powergate_lanes()
1448 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); in chv_phy_powergate_lanes()
1453 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, in chv_pipe_power_well_enabled() argument
1460 mutex_lock(&dev_priv->pcu_lock); in chv_pipe_power_well_enabled()
1462 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); in chv_pipe_power_well_enabled()
1474 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); in chv_pipe_power_well_enabled()
1477 mutex_unlock(&dev_priv->pcu_lock); in chv_pipe_power_well_enabled()
1482 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, in chv_set_pipe_power_well() argument
1492 mutex_lock(&dev_priv->pcu_lock); in chv_set_pipe_power_well()
1495 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) in chv_set_pipe_power_well()
1500 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); in chv_set_pipe_power_well()
1503 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); in chv_set_pipe_power_well()
1508 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); in chv_set_pipe_power_well()
1513 mutex_unlock(&dev_priv->pcu_lock); in chv_set_pipe_power_well()
1516 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, in chv_pipe_power_well_enable() argument
1521 chv_set_pipe_power_well(dev_priv, power_well, true); in chv_pipe_power_well_enable()
1523 vlv_display_power_well_init(dev_priv); in chv_pipe_power_well_enable()
1526 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, in chv_pipe_power_well_disable() argument
1531 vlv_display_power_well_deinit(dev_priv); in chv_pipe_power_well_disable()
1533 chv_set_pipe_power_well(dev_priv, power_well, false); in chv_pipe_power_well_disable()
1537 __intel_display_power_get_domain(struct drm_i915_private *dev_priv, in __intel_display_power_get_domain() argument
1540 struct i915_power_domains *power_domains = &dev_priv->power_domains; in __intel_display_power_get_domain()
1543 for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain)) in __intel_display_power_get_domain()
1544 intel_power_well_get(dev_priv, power_well); in __intel_display_power_get_domain()
1561 void intel_display_power_get(struct drm_i915_private *dev_priv, in intel_display_power_get() argument
1564 struct i915_power_domains *power_domains = &dev_priv->power_domains; in intel_display_power_get()
1566 intel_runtime_pm_get(dev_priv); in intel_display_power_get()
1570 __intel_display_power_get_domain(dev_priv, domain); in intel_display_power_get()
1587 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, in intel_display_power_get_if_enabled() argument
1590 struct i915_power_domains *power_domains = &dev_priv->power_domains; in intel_display_power_get_if_enabled()
1593 if (!intel_runtime_pm_get_if_in_use(dev_priv)) in intel_display_power_get_if_enabled()
1598 if (__intel_display_power_is_enabled(dev_priv, domain)) { in intel_display_power_get_if_enabled()
1599 __intel_display_power_get_domain(dev_priv, domain); in intel_display_power_get_if_enabled()
1608 intel_runtime_pm_put(dev_priv); in intel_display_power_get_if_enabled()
1622 void intel_display_power_put(struct drm_i915_private *dev_priv, in intel_display_power_put() argument
1628 power_domains = &dev_priv->power_domains; in intel_display_power_put()
1637 for_each_power_domain_well_rev(dev_priv, power_well, BIT_ULL(domain)) in intel_display_power_put()
1638 intel_power_well_put(dev_priv, power_well); in intel_display_power_put()
1642 intel_runtime_pm_put(dev_priv); in intel_display_power_put()
2271 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, in intel_display_power_well_is_enabled() argument
2277 power_well = lookup_power_well(dev_priv, power_well_id); in intel_display_power_well_is_enabled()
2278 ret = power_well->ops->is_enabled(dev_priv, power_well); in intel_display_power_well_is_enabled()
2754 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, in sanitize_disable_power_well_option() argument
2763 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, in get_allowed_dc_mask() argument
2770 if (IS_GEN9_BC(dev_priv) || INTEL_INFO(dev_priv)->gen >= 10) { in get_allowed_dc_mask()
2773 } else if (IS_GEN9_LP(dev_priv)) { in get_allowed_dc_mask()
2812 static void assert_power_well_ids_unique(struct drm_i915_private *dev_priv) in assert_power_well_ids_unique() argument
2814 struct i915_power_domains *power_domains = &dev_priv->power_domains; in assert_power_well_ids_unique()
2840 int intel_power_domains_init(struct drm_i915_private *dev_priv) in intel_power_domains_init() argument
2842 struct i915_power_domains *power_domains = &dev_priv->power_domains; in intel_power_domains_init()
2845 sanitize_disable_power_well_option(dev_priv, in intel_power_domains_init()
2847 dev_priv->csr.allowed_dc_mask = in intel_power_domains_init()
2848 get_allowed_dc_mask(dev_priv, i915_modparams.enable_dc); in intel_power_domains_init()
2858 if (IS_ICELAKE(dev_priv)) { in intel_power_domains_init()
2860 } else if (IS_HASWELL(dev_priv)) { in intel_power_domains_init()
2862 } else if (IS_BROADWELL(dev_priv)) { in intel_power_domains_init()
2864 } else if (IS_GEN9_BC(dev_priv)) { in intel_power_domains_init()
2866 } else if (IS_CANNONLAKE(dev_priv)) { in intel_power_domains_init()
2875 if (!IS_CNL_WITH_PORT_F(dev_priv)) in intel_power_domains_init()
2878 } else if (IS_BROXTON(dev_priv)) { in intel_power_domains_init()
2880 } else if (IS_GEMINILAKE(dev_priv)) { in intel_power_domains_init()
2882 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_power_domains_init()
2884 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_power_domains_init()
2886 } else if (IS_I830(dev_priv)) { in intel_power_domains_init()
2892 assert_power_well_ids_unique(dev_priv); in intel_power_domains_init()
2905 void intel_power_domains_fini(struct drm_i915_private *dev_priv) in intel_power_domains_fini() argument
2907 struct device *kdev = &dev_priv->drm.pdev->dev; in intel_power_domains_fini()
2918 intel_display_set_init_power(dev_priv, true); in intel_power_domains_fini()
2922 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); in intel_power_domains_fini()
2928 if (!HAS_RUNTIME_PM(dev_priv)) in intel_power_domains_fini()
2932 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) in intel_power_domains_sync_hw() argument
2934 struct i915_power_domains *power_domains = &dev_priv->power_domains; in intel_power_domains_sync_hw()
2938 for_each_power_well(dev_priv, power_well) { in intel_power_domains_sync_hw()
2939 power_well->ops->sync_hw(dev_priv, power_well); in intel_power_domains_sync_hw()
2940 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, in intel_power_domains_sync_hw()
2947 bool intel_dbuf_slice_set(struct drm_i915_private *dev_priv, in intel_dbuf_slice_set() argument
2967 static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) in gen9_dbuf_enable() argument
2969 intel_dbuf_slice_set(dev_priv, DBUF_CTL, true); in gen9_dbuf_enable()
2972 static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) in gen9_dbuf_disable() argument
2974 intel_dbuf_slice_set(dev_priv, DBUF_CTL, false); in gen9_dbuf_disable()
2977 static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv) in intel_dbuf_max_slices() argument
2979 if (INTEL_GEN(dev_priv) < 11) in intel_dbuf_max_slices()
2984 void icl_dbuf_slices_update(struct drm_i915_private *dev_priv, in icl_dbuf_slices_update() argument
2987 u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; in icl_dbuf_slices_update()
2991 if (req_slices > intel_dbuf_max_slices(dev_priv)) { in icl_dbuf_slices_update()
3001 ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true); in icl_dbuf_slices_update()
3003 ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false); in icl_dbuf_slices_update()
3006 dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices; in icl_dbuf_slices_update()
3009 static void icl_dbuf_enable(struct drm_i915_private *dev_priv) in icl_dbuf_enable() argument
3021 dev_priv->wm.skl_hw.ddb.enabled_slices = 2; in icl_dbuf_enable()
3024 static void icl_dbuf_disable(struct drm_i915_private *dev_priv) in icl_dbuf_disable() argument
3036 dev_priv->wm.skl_hw.ddb.enabled_slices = 0; in icl_dbuf_disable()
3039 static void icl_mbus_init(struct drm_i915_private *dev_priv) in icl_mbus_init() argument
3051 static void skl_display_core_init(struct drm_i915_private *dev_priv, in skl_display_core_init() argument
3054 struct i915_power_domains *power_domains = &dev_priv->power_domains; in skl_display_core_init()
3058 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in skl_display_core_init()
3067 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in skl_display_core_init()
3068 intel_power_well_enable(dev_priv, well); in skl_display_core_init()
3070 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); in skl_display_core_init()
3071 intel_power_well_enable(dev_priv, well); in skl_display_core_init()
3075 skl_init_cdclk(dev_priv); in skl_display_core_init()
3077 gen9_dbuf_enable(dev_priv); in skl_display_core_init()
3079 if (resume && dev_priv->csr.dmc_payload) in skl_display_core_init()
3080 intel_csr_load_program(dev_priv); in skl_display_core_init()
3083 static void skl_display_core_uninit(struct drm_i915_private *dev_priv) in skl_display_core_uninit() argument
3085 struct i915_power_domains *power_domains = &dev_priv->power_domains; in skl_display_core_uninit()
3088 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in skl_display_core_uninit()
3090 gen9_dbuf_disable(dev_priv); in skl_display_core_uninit()
3092 skl_uninit_cdclk(dev_priv); in skl_display_core_uninit()
3105 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in skl_display_core_uninit()
3106 intel_power_well_disable(dev_priv, well); in skl_display_core_uninit()
3113 void bxt_display_core_init(struct drm_i915_private *dev_priv, in bxt_display_core_init() argument
3116 struct i915_power_domains *power_domains = &dev_priv->power_domains; in bxt_display_core_init()
3120 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in bxt_display_core_init()
3135 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in bxt_display_core_init()
3136 intel_power_well_enable(dev_priv, well); in bxt_display_core_init()
3140 bxt_init_cdclk(dev_priv); in bxt_display_core_init()
3142 gen9_dbuf_enable(dev_priv); in bxt_display_core_init()
3144 if (resume && dev_priv->csr.dmc_payload) in bxt_display_core_init()
3145 intel_csr_load_program(dev_priv); in bxt_display_core_init()
3148 void bxt_display_core_uninit(struct drm_i915_private *dev_priv) in bxt_display_core_uninit() argument
3150 struct i915_power_domains *power_domains = &dev_priv->power_domains; in bxt_display_core_uninit()
3153 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in bxt_display_core_uninit()
3155 gen9_dbuf_disable(dev_priv); in bxt_display_core_uninit()
3157 bxt_uninit_cdclk(dev_priv); in bxt_display_core_uninit()
3168 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in bxt_display_core_uninit()
3169 intel_power_well_disable(dev_priv, well); in bxt_display_core_uninit()
3205 static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv, in cnl_set_procmon_ref_values() argument
3242 static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume) in cnl_display_core_init() argument
3244 struct i915_power_domains *power_domains = &dev_priv->power_domains; in cnl_display_core_init()
3248 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in cnl_display_core_init()
3261 cnl_set_procmon_ref_values(dev_priv, PORT_A); in cnl_display_core_init()
3277 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in cnl_display_core_init()
3278 intel_power_well_enable(dev_priv, well); in cnl_display_core_init()
3282 cnl_init_cdclk(dev_priv); in cnl_display_core_init()
3285 gen9_dbuf_enable(dev_priv); in cnl_display_core_init()
3287 if (resume && dev_priv->csr.dmc_payload) in cnl_display_core_init()
3288 intel_csr_load_program(dev_priv); in cnl_display_core_init()
3291 static void cnl_display_core_uninit(struct drm_i915_private *dev_priv) in cnl_display_core_uninit() argument
3293 struct i915_power_domains *power_domains = &dev_priv->power_domains; in cnl_display_core_uninit()
3297 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in cnl_display_core_uninit()
3302 gen9_dbuf_disable(dev_priv); in cnl_display_core_uninit()
3305 cnl_uninit_cdclk(dev_priv); in cnl_display_core_uninit()
3313 well = lookup_power_well(dev_priv, SKL_DISP_PW_1); in cnl_display_core_uninit()
3314 intel_power_well_disable(dev_priv, well); in cnl_display_core_uninit()
3325 static void icl_display_core_init(struct drm_i915_private *dev_priv, in icl_display_core_init() argument
3328 struct i915_power_domains *power_domains = &dev_priv->power_domains; in icl_display_core_init()
3333 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in icl_display_core_init()
3346 cnl_set_procmon_ref_values(dev_priv, port); in icl_display_core_init()
3363 well = lookup_power_well(dev_priv, ICL_DISP_PW_1); in icl_display_core_init()
3364 intel_power_well_enable(dev_priv, well); in icl_display_core_init()
3368 icl_init_cdclk(dev_priv); in icl_display_core_init()
3371 icl_dbuf_enable(dev_priv); in icl_display_core_init()
3374 icl_mbus_init(dev_priv); in icl_display_core_init()
3381 static void icl_display_core_uninit(struct drm_i915_private *dev_priv) in icl_display_core_uninit() argument
3383 struct i915_power_domains *power_domains = &dev_priv->power_domains; in icl_display_core_uninit()
3388 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); in icl_display_core_uninit()
3393 icl_dbuf_disable(dev_priv); in icl_display_core_uninit()
3396 icl_uninit_cdclk(dev_priv); in icl_display_core_uninit()
3404 well = lookup_power_well(dev_priv, ICL_DISP_PW_1); in icl_display_core_uninit()
3405 intel_power_well_disable(dev_priv, well); in icl_display_core_uninit()
3416 static void chv_phy_control_init(struct drm_i915_private *dev_priv) in chv_phy_control_init() argument
3419 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); in chv_phy_control_init()
3421 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); in chv_phy_control_init()
3430 dev_priv->chv_phy_control = in chv_phy_control_init()
3444 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { in chv_phy_control_init()
3452 dev_priv->chv_phy_control |= in chv_phy_control_init()
3455 dev_priv->chv_phy_control |= in chv_phy_control_init()
3462 dev_priv->chv_phy_control |= in chv_phy_control_init()
3465 dev_priv->chv_phy_control |= in chv_phy_control_init()
3468 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); in chv_phy_control_init()
3470 dev_priv->chv_phy_assert[DPIO_PHY0] = false; in chv_phy_control_init()
3472 dev_priv->chv_phy_assert[DPIO_PHY0] = true; in chv_phy_control_init()
3475 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { in chv_phy_control_init()
3484 dev_priv->chv_phy_control |= in chv_phy_control_init()
3487 dev_priv->chv_phy_control |= in chv_phy_control_init()
3490 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); in chv_phy_control_init()
3492 dev_priv->chv_phy_assert[DPIO_PHY1] = false; in chv_phy_control_init()
3494 dev_priv->chv_phy_assert[DPIO_PHY1] = true; in chv_phy_control_init()
3497 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); in chv_phy_control_init()
3500 dev_priv->chv_phy_control); in chv_phy_control_init()
3503 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) in vlv_cmnlane_wa() argument
3506 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); in vlv_cmnlane_wa()
3508 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); in vlv_cmnlane_wa()
3511 if (cmn->ops->is_enabled(dev_priv, cmn) && in vlv_cmnlane_wa()
3512 disp2d->ops->is_enabled(dev_priv, disp2d) && in vlv_cmnlane_wa()
3519 disp2d->ops->enable(dev_priv, disp2d); in vlv_cmnlane_wa()
3528 cmn->ops->disable(dev_priv, cmn); in vlv_cmnlane_wa()
3542 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) in intel_power_domains_init_hw() argument
3544 struct i915_power_domains *power_domains = &dev_priv->power_domains; in intel_power_domains_init_hw()
3548 if (IS_ICELAKE(dev_priv)) { in intel_power_domains_init_hw()
3549 icl_display_core_init(dev_priv, resume); in intel_power_domains_init_hw()
3550 } else if (IS_CANNONLAKE(dev_priv)) { in intel_power_domains_init_hw()
3551 cnl_display_core_init(dev_priv, resume); in intel_power_domains_init_hw()
3552 } else if (IS_GEN9_BC(dev_priv)) { in intel_power_domains_init_hw()
3553 skl_display_core_init(dev_priv, resume); in intel_power_domains_init_hw()
3554 } else if (IS_GEN9_LP(dev_priv)) { in intel_power_domains_init_hw()
3555 bxt_display_core_init(dev_priv, resume); in intel_power_domains_init_hw()
3556 } else if (IS_CHERRYVIEW(dev_priv)) { in intel_power_domains_init_hw()
3558 chv_phy_control_init(dev_priv); in intel_power_domains_init_hw()
3560 } else if (IS_VALLEYVIEW(dev_priv)) { in intel_power_domains_init_hw()
3562 vlv_cmnlane_wa(dev_priv); in intel_power_domains_init_hw()
3567 intel_display_set_init_power(dev_priv, true); in intel_power_domains_init_hw()
3570 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); in intel_power_domains_init_hw()
3571 intel_power_domains_sync_hw(dev_priv); in intel_power_domains_init_hw()
3582 void intel_power_domains_suspend(struct drm_i915_private *dev_priv) in intel_power_domains_suspend() argument
3589 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); in intel_power_domains_suspend()
3591 if (IS_ICELAKE(dev_priv)) in intel_power_domains_suspend()
3592 icl_display_core_uninit(dev_priv); in intel_power_domains_suspend()
3593 else if (IS_CANNONLAKE(dev_priv)) in intel_power_domains_suspend()
3594 cnl_display_core_uninit(dev_priv); in intel_power_domains_suspend()
3595 else if (IS_GEN9_BC(dev_priv)) in intel_power_domains_suspend()
3596 skl_display_core_uninit(dev_priv); in intel_power_domains_suspend()
3597 else if (IS_GEN9_LP(dev_priv)) in intel_power_domains_suspend()
3598 bxt_display_core_uninit(dev_priv); in intel_power_domains_suspend()
3601 static void intel_power_domains_dump_info(struct drm_i915_private *dev_priv) in intel_power_domains_dump_info() argument
3603 struct i915_power_domains *power_domains = &dev_priv->power_domains; in intel_power_domains_dump_info()
3606 for_each_power_well(dev_priv, power_well) { in intel_power_domains_dump_info()
3629 void intel_power_domains_verify_state(struct drm_i915_private *dev_priv) in intel_power_domains_verify_state() argument
3631 struct i915_power_domains *power_domains = &dev_priv->power_domains; in intel_power_domains_verify_state()
3638 for_each_power_well(dev_priv, power_well) { in intel_power_domains_verify_state()
3651 enabled = power_well->ops->is_enabled(dev_priv, power_well); in intel_power_domains_verify_state()
3673 intel_power_domains_dump_info(dev_priv); in intel_power_domains_verify_state()
3691 void intel_runtime_pm_get(struct drm_i915_private *dev_priv) in intel_runtime_pm_get() argument
3693 struct pci_dev *pdev = dev_priv->drm.pdev; in intel_runtime_pm_get()
3700 atomic_inc(&dev_priv->runtime_pm.wakeref_count); in intel_runtime_pm_get()
3701 assert_rpm_wakelock_held(dev_priv); in intel_runtime_pm_get()
3717 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv) in intel_runtime_pm_get_if_in_use() argument
3720 struct pci_dev *pdev = dev_priv->drm.pdev; in intel_runtime_pm_get_if_in_use()
3733 atomic_inc(&dev_priv->runtime_pm.wakeref_count); in intel_runtime_pm_get_if_in_use()
3734 assert_rpm_wakelock_held(dev_priv); in intel_runtime_pm_get_if_in_use()
3756 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) in intel_runtime_pm_get_noresume() argument
3758 struct pci_dev *pdev = dev_priv->drm.pdev; in intel_runtime_pm_get_noresume()
3761 assert_rpm_wakelock_held(dev_priv); in intel_runtime_pm_get_noresume()
3764 atomic_inc(&dev_priv->runtime_pm.wakeref_count); in intel_runtime_pm_get_noresume()
3775 void intel_runtime_pm_put(struct drm_i915_private *dev_priv) in intel_runtime_pm_put() argument
3777 struct pci_dev *pdev = dev_priv->drm.pdev; in intel_runtime_pm_put()
3780 assert_rpm_wakelock_held(dev_priv); in intel_runtime_pm_put()
3781 atomic_dec(&dev_priv->runtime_pm.wakeref_count); in intel_runtime_pm_put()
3797 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) in intel_runtime_pm_enable() argument
3799 struct pci_dev *pdev = dev_priv->drm.pdev; in intel_runtime_pm_enable()
3811 if (!HAS_RUNTIME_PM(dev_priv)) { in intel_runtime_pm_enable()