1152 	if (!dev_priv->chv_phy_assert[DPIO_PHY1])  in assert_chv_phy_status()
1153 		phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |  in assert_chv_phy_status()
1154 				     PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |  in assert_chv_phy_status()
1155 				     PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));  in assert_chv_phy_status()
1199 		phy_status |= PHY_POWERGOOD(DPIO_PHY1);  in assert_chv_phy_status()
1202 		if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)  in assert_chv_phy_status()
1203 			phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);  in assert_chv_phy_status()
1206 			     PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))  in assert_chv_phy_status()
1207 			phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);  in assert_chv_phy_status()
1210 			     PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))  in assert_chv_phy_status()
1211 			phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);  in assert_chv_phy_status()
1213 			     PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))  in assert_chv_phy_status()
1214 			phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);  in assert_chv_phy_status()
1250 		phy = DPIO_PHY1;  in chv_dpio_cmn_power_well_enable()
1312 		phy = DPIO_PHY1;  in chv_dpio_cmn_power_well_disable()
2391 			.bxt.phy = DPIO_PHY1,
2446 			.bxt.phy = DPIO_PHY1,
3432 		PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |  in chv_phy_control_init()
3435 		PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);  in chv_phy_control_init()
3485 				PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);  in chv_phy_control_init()
3488 			PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);  in chv_phy_control_init()
3490 		dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);  in chv_phy_control_init()
3492 		dev_priv->chv_phy_assert[DPIO_PHY1] = false;  in chv_phy_control_init()
3494 		dev_priv->chv_phy_assert[DPIO_PHY1] = true;  in chv_phy_control_init()