Lines Matching refs:engine
182 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; in intel_emit_post_sync_nonzero_flush()
216 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; in gen6_render_ring_flush()
286 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; in gen7_render_ring_flush()
344 static void ring_setup_phys_status_page(struct intel_engine_cs *engine) in ring_setup_phys_status_page() argument
346 struct drm_i915_private *dev_priv = engine->i915; in ring_setup_phys_status_page()
355 static void intel_ring_setup_status_page(struct intel_engine_cs *engine) in intel_ring_setup_status_page() argument
357 struct drm_i915_private *dev_priv = engine->i915; in intel_ring_setup_status_page()
364 switch (engine->id) { in intel_ring_setup_status_page()
370 GEM_BUG_ON(engine->id); in intel_ring_setup_status_page()
385 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); in intel_ring_setup_status_page()
387 mmio = RING_HWS_PGA(engine->mmio_base); in intel_ring_setup_status_page()
397 if (engine->id == RCS) in intel_ring_setup_status_page()
400 I915_WRITE(RING_HWSTAM(engine->mmio_base), mask); in intel_ring_setup_status_page()
403 I915_WRITE(mmio, engine->status_page.ggtt_offset); in intel_ring_setup_status_page()
408 i915_reg_t reg = RING_INSTPM(engine->mmio_base); in intel_ring_setup_status_page()
411 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); in intel_ring_setup_status_page()
420 engine->name); in intel_ring_setup_status_page()
424 static bool stop_ring(struct intel_engine_cs *engine) in stop_ring() argument
426 struct drm_i915_private *dev_priv = engine->i915; in stop_ring()
429 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); in stop_ring()
431 RING_MI_MODE(engine->mmio_base), in stop_ring()
436 engine->name); in stop_ring()
441 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) in stop_ring()
446 I915_WRITE_HEAD(engine, I915_READ_TAIL(engine)); in stop_ring()
448 I915_WRITE_HEAD(engine, 0); in stop_ring()
449 I915_WRITE_TAIL(engine, 0); in stop_ring()
452 I915_WRITE_CTL(engine, 0); in stop_ring()
454 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; in stop_ring()
457 static int init_ring_common(struct intel_engine_cs *engine) in init_ring_common() argument
459 struct drm_i915_private *dev_priv = engine->i915; in init_ring_common()
460 struct intel_ring *ring = engine->buffer; in init_ring_common()
465 if (!stop_ring(engine)) { in init_ring_common()
469 engine->name, in init_ring_common()
470 I915_READ_CTL(engine), in init_ring_common()
471 I915_READ_HEAD(engine), in init_ring_common()
472 I915_READ_TAIL(engine), in init_ring_common()
473 I915_READ_START(engine)); in init_ring_common()
475 if (!stop_ring(engine)) { in init_ring_common()
478 engine->name, in init_ring_common()
479 I915_READ_CTL(engine), in init_ring_common()
480 I915_READ_HEAD(engine), in init_ring_common()
481 I915_READ_TAIL(engine), in init_ring_common()
482 I915_READ_START(engine)); in init_ring_common()
489 ring_setup_phys_status_page(engine); in init_ring_common()
491 intel_ring_setup_status_page(engine); in init_ring_common()
493 intel_engine_reset_breadcrumbs(engine); in init_ring_common()
496 I915_READ_HEAD(engine); in init_ring_common()
502 I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); in init_ring_common()
505 if (I915_READ_HEAD(engine)) in init_ring_common()
507 engine->name, I915_READ_HEAD(engine)); in init_ring_common()
514 I915_WRITE_HEAD(engine, ring->head); in init_ring_common()
515 I915_WRITE_TAIL(engine, ring->tail); in init_ring_common()
516 (void)I915_READ_TAIL(engine); in init_ring_common()
518 I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID); in init_ring_common()
521 if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base), in init_ring_common()
526 engine->name, in init_ring_common()
527 I915_READ_CTL(engine), in init_ring_common()
528 I915_READ_CTL(engine) & RING_VALID, in init_ring_common()
529 I915_READ_HEAD(engine), ring->head, in init_ring_common()
530 I915_READ_TAIL(engine), ring->tail, in init_ring_common()
531 I915_READ_START(engine), in init_ring_common()
538 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); in init_ring_common()
546 static struct i915_request *reset_prepare(struct intel_engine_cs *engine) in reset_prepare() argument
548 intel_engine_stop_cs(engine); in reset_prepare()
550 if (engine->irq_seqno_barrier) in reset_prepare()
551 engine->irq_seqno_barrier(engine); in reset_prepare()
553 return i915_gem_find_active_request(engine); in reset_prepare()
570 static void reset_ring(struct intel_engine_cs *engine, struct i915_request *rq) in reset_ring() argument
572 GEM_TRACE("%s seqno=%x\n", engine->name, rq ? rq->global_seqno : 0); in reset_ring()
596 static void reset_finish(struct intel_engine_cs *engine) in reset_finish() argument
615 static int init_render_ring(struct intel_engine_cs *engine) in init_render_ring() argument
617 struct drm_i915_private *dev_priv = engine->i915; in init_render_ring()
618 int ret = init_ring_common(engine); in init_render_ring()
622 intel_whitelist_workarounds_apply(engine); in init_render_ring()
663 I915_WRITE_IMR(engine, ~engine->irq_keep_mask); in init_render_ring()
671 struct intel_engine_cs *engine; in gen6_signal() local
675 for_each_engine(engine, dev_priv, id) { in gen6_signal()
678 if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) in gen6_signal()
681 mbox_reg = rq->engine->semaphore.mbox.signal[engine->hw_id]; in gen6_signal()
695 static void cancel_requests(struct intel_engine_cs *engine) in cancel_requests() argument
700 spin_lock_irqsave(&engine->timeline.lock, flags); in cancel_requests()
703 list_for_each_entry(request, &engine->timeline.requests, link) { in cancel_requests()
710 spin_unlock_irqrestore(&engine->timeline.lock, flags); in cancel_requests()
719 I915_WRITE_TAIL(request->engine, in i9xx_submit_request()
738 return i9xx_emit_breadcrumb(rq, rq->engine->semaphore.signal(rq, cs)); in gen6_sema_emit_breadcrumb()
747 u32 wait_mbox = signal->engine->semaphore.mbox.wait[rq->engine->hw_id]; in gen6_ring_sync_to()
770 gen5_seqno_barrier(struct intel_engine_cs *engine) in gen5_seqno_barrier() argument
788 gen6_seqno_barrier(struct intel_engine_cs *engine) in gen6_seqno_barrier() argument
790 struct drm_i915_private *dev_priv = engine->i915; in gen6_seqno_barrier()
808 POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); in gen6_seqno_barrier()
813 gen5_irq_enable(struct intel_engine_cs *engine) in gen5_irq_enable() argument
815 gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); in gen5_irq_enable()
819 gen5_irq_disable(struct intel_engine_cs *engine) in gen5_irq_disable() argument
821 gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); in gen5_irq_disable()
825 i9xx_irq_enable(struct intel_engine_cs *engine) in i9xx_irq_enable() argument
827 struct drm_i915_private *dev_priv = engine->i915; in i9xx_irq_enable()
829 dev_priv->irq_mask &= ~engine->irq_enable_mask; in i9xx_irq_enable()
831 POSTING_READ_FW(RING_IMR(engine->mmio_base)); in i9xx_irq_enable()
835 i9xx_irq_disable(struct intel_engine_cs *engine) in i9xx_irq_disable() argument
837 struct drm_i915_private *dev_priv = engine->i915; in i9xx_irq_disable()
839 dev_priv->irq_mask |= engine->irq_enable_mask; in i9xx_irq_disable()
844 i8xx_irq_enable(struct intel_engine_cs *engine) in i8xx_irq_enable() argument
846 struct drm_i915_private *dev_priv = engine->i915; in i8xx_irq_enable()
848 dev_priv->irq_mask &= ~engine->irq_enable_mask; in i8xx_irq_enable()
850 POSTING_READ16(RING_IMR(engine->mmio_base)); in i8xx_irq_enable()
854 i8xx_irq_disable(struct intel_engine_cs *engine) in i8xx_irq_disable() argument
856 struct drm_i915_private *dev_priv = engine->i915; in i8xx_irq_disable()
858 dev_priv->irq_mask |= engine->irq_enable_mask; in i8xx_irq_disable()
878 gen6_irq_enable(struct intel_engine_cs *engine) in gen6_irq_enable() argument
880 struct drm_i915_private *dev_priv = engine->i915; in gen6_irq_enable()
882 I915_WRITE_IMR(engine, in gen6_irq_enable()
883 ~(engine->irq_enable_mask | in gen6_irq_enable()
884 engine->irq_keep_mask)); in gen6_irq_enable()
885 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); in gen6_irq_enable()
889 gen6_irq_disable(struct intel_engine_cs *engine) in gen6_irq_disable() argument
891 struct drm_i915_private *dev_priv = engine->i915; in gen6_irq_disable()
893 I915_WRITE_IMR(engine, ~engine->irq_keep_mask); in gen6_irq_disable()
894 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); in gen6_irq_disable()
898 hsw_vebox_irq_enable(struct intel_engine_cs *engine) in hsw_vebox_irq_enable() argument
900 struct drm_i915_private *dev_priv = engine->i915; in hsw_vebox_irq_enable()
902 I915_WRITE_IMR(engine, ~engine->irq_enable_mask); in hsw_vebox_irq_enable()
903 gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask); in hsw_vebox_irq_enable()
907 hsw_vebox_irq_disable(struct intel_engine_cs *engine) in hsw_vebox_irq_disable() argument
909 struct drm_i915_private *dev_priv = engine->i915; in hsw_vebox_irq_disable()
911 I915_WRITE_IMR(engine, ~0); in hsw_vebox_irq_disable()
912 gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask); in hsw_vebox_irq_disable()
943 u32 *cs, cs_offset = i915_ggtt_offset(rq->engine->scratch); in i830_emit_bb_start()
1129 intel_engine_create_ring(struct intel_engine_cs *engine, in intel_engine_create_ring() argument
1138 GEM_BUG_ON(timeline == &engine->timeline); in intel_engine_create_ring()
1139 lockdep_assert_held(&engine->i915->drm.struct_mutex); in intel_engine_create_ring()
1154 if (IS_I830(engine->i915) || IS_I845G(engine->i915)) in intel_engine_create_ring()
1159 vma = intel_ring_create_vma(engine->i915, size); in intel_engine_create_ring()
1268 alloc_context_vma(struct intel_engine_cs *engine) in alloc_context_vma() argument
1270 struct drm_i915_private *i915 = engine->i915; in alloc_context_vma()
1275 obj = i915_gem_object_create(i915, engine->context_size); in alloc_context_vma()
1279 if (engine->default_state) { in alloc_context_vma()
1288 defaults = i915_gem_object_pin_map(engine->default_state, in alloc_context_vma()
1295 memcpy(vaddr, defaults, engine->context_size); in alloc_context_vma()
1297 i915_gem_object_unpin_map(engine->default_state); in alloc_context_vma()
1337 __ring_context_pin(struct intel_engine_cs *engine, in __ring_context_pin() argument
1343 if (!ce->state && engine->context_size) { in __ring_context_pin()
1346 vma = alloc_context_vma(engine); in __ring_context_pin()
1366 GEM_BUG_ON(!engine->buffer); in __ring_context_pin()
1367 ce->ring = engine->buffer; in __ring_context_pin()
1384 intel_ring_context_pin(struct intel_engine_cs *engine, in intel_ring_context_pin() argument
1387 struct intel_context *ce = to_intel_context(ctx, engine); in intel_ring_context_pin()
1397 return __ring_context_pin(engine, ctx, ce); in intel_ring_context_pin()
1400 static int intel_init_ring_buffer(struct intel_engine_cs *engine) in intel_init_ring_buffer() argument
1407 intel_engine_setup_common(engine); in intel_init_ring_buffer()
1409 timeline = i915_timeline_create(engine->i915, engine->name); in intel_init_ring_buffer()
1415 ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE); in intel_init_ring_buffer()
1423 err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE); in intel_init_ring_buffer()
1427 GEM_BUG_ON(engine->buffer); in intel_init_ring_buffer()
1428 engine->buffer = ring; in intel_init_ring_buffer()
1431 if (HAS_BROKEN_CS_TLB(engine->i915)) in intel_init_ring_buffer()
1433 err = intel_engine_create_scratch(engine, size); in intel_init_ring_buffer()
1437 err = intel_engine_init_common(engine); in intel_init_ring_buffer()
1444 intel_engine_cleanup_scratch(engine); in intel_init_ring_buffer()
1450 intel_engine_cleanup_common(engine); in intel_init_ring_buffer()
1454 void intel_engine_cleanup(struct intel_engine_cs *engine) in intel_engine_cleanup() argument
1456 struct drm_i915_private *dev_priv = engine->i915; in intel_engine_cleanup()
1459 (I915_READ_MODE(engine) & MODE_IDLE) == 0); in intel_engine_cleanup()
1461 intel_ring_unpin(engine->buffer); in intel_engine_cleanup()
1462 intel_ring_free(engine->buffer); in intel_engine_cleanup()
1464 if (engine->cleanup) in intel_engine_cleanup()
1465 engine->cleanup(engine); in intel_engine_cleanup()
1467 intel_engine_cleanup_common(engine); in intel_engine_cleanup()
1469 dev_priv->engine[engine->id] = NULL; in intel_engine_cleanup()
1470 kfree(engine); in intel_engine_cleanup()
1475 struct intel_engine_cs *engine; in intel_legacy_submission_resume() local
1479 for_each_engine(engine, dev_priv, id) in intel_legacy_submission_resume()
1480 intel_ring_reset(engine->buffer, 0); in intel_legacy_submission_resume()
1486 const struct intel_engine_cs * const engine = rq->engine; in load_pd_dir() local
1494 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine)); in load_pd_dir()
1498 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); in load_pd_dir()
1508 const struct intel_engine_cs * const engine = rq->engine; in flush_pd_dir() local
1517 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); in flush_pd_dir()
1518 *cs++ = i915_ggtt_offset(engine->scratch); in flush_pd_dir()
1528 struct intel_engine_cs *engine = rq->engine; in mi_set_context() local
1568 if (signaller == engine) in mi_set_context()
1594 engine)->state) | in mi_set_context()
1615 if (signaller == engine) in mi_set_context()
1627 *cs++ = i915_ggtt_offset(engine->scratch); in mi_set_context()
1668 struct intel_engine_cs *engine = rq->engine; in switch_context() local
1683 if (intel_engine_flag(engine) & ppgtt->pd_dirty_rings) { in switch_context()
1684 unwind_mm = intel_engine_flag(engine); in switch_context()
1691 GEM_BUG_ON(engine->id != RCS); in switch_context()
2062 struct intel_engine_cs *engine) in intel_ring_init_semaphores() argument
2070 engine->semaphore.sync_to = gen6_ring_sync_to; in intel_ring_init_semaphores()
2071 engine->semaphore.signal = gen6_signal; in intel_ring_init_semaphores()
2108 if (i == engine->hw_id) { in intel_ring_init_semaphores()
2112 wait_mbox = sem_data[engine->hw_id][i].wait_mbox; in intel_ring_init_semaphores()
2113 mbox_reg = sem_data[engine->hw_id][i].mbox_reg; in intel_ring_init_semaphores()
2116 engine->semaphore.mbox.wait[i] = wait_mbox; in intel_ring_init_semaphores()
2117 engine->semaphore.mbox.signal[i] = mbox_reg; in intel_ring_init_semaphores()
2122 struct intel_engine_cs *engine) in intel_ring_init_irq() argument
2125 engine->irq_enable = gen6_irq_enable; in intel_ring_init_irq()
2126 engine->irq_disable = gen6_irq_disable; in intel_ring_init_irq()
2127 engine->irq_seqno_barrier = gen6_seqno_barrier; in intel_ring_init_irq()
2129 engine->irq_enable = gen5_irq_enable; in intel_ring_init_irq()
2130 engine->irq_disable = gen5_irq_disable; in intel_ring_init_irq()
2131 engine->irq_seqno_barrier = gen5_seqno_barrier; in intel_ring_init_irq()
2133 engine->irq_enable = i9xx_irq_enable; in intel_ring_init_irq()
2134 engine->irq_disable = i9xx_irq_disable; in intel_ring_init_irq()
2136 engine->irq_enable = i8xx_irq_enable; in intel_ring_init_irq()
2137 engine->irq_disable = i8xx_irq_disable; in intel_ring_init_irq()
2141 static void i9xx_set_default_submission(struct intel_engine_cs *engine) in i9xx_set_default_submission() argument
2143 engine->submit_request = i9xx_submit_request; in i9xx_set_default_submission()
2144 engine->cancel_requests = cancel_requests; in i9xx_set_default_submission()
2146 engine->park = NULL; in i9xx_set_default_submission()
2147 engine->unpark = NULL; in i9xx_set_default_submission()
2150 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) in gen6_bsd_set_default_submission() argument
2152 i9xx_set_default_submission(engine); in gen6_bsd_set_default_submission()
2153 engine->submit_request = gen6_bsd_submit_request; in gen6_bsd_set_default_submission()
2157 struct intel_engine_cs *engine) in intel_ring_default_vfuncs() argument
2162 intel_ring_init_irq(dev_priv, engine); in intel_ring_default_vfuncs()
2163 intel_ring_init_semaphores(dev_priv, engine); in intel_ring_default_vfuncs()
2165 engine->init_hw = init_ring_common; in intel_ring_default_vfuncs()
2166 engine->reset.prepare = reset_prepare; in intel_ring_default_vfuncs()
2167 engine->reset.reset = reset_ring; in intel_ring_default_vfuncs()
2168 engine->reset.finish = reset_finish; in intel_ring_default_vfuncs()
2170 engine->context_pin = intel_ring_context_pin; in intel_ring_default_vfuncs()
2171 engine->request_alloc = ring_request_alloc; in intel_ring_default_vfuncs()
2173 engine->emit_breadcrumb = i9xx_emit_breadcrumb; in intel_ring_default_vfuncs()
2174 engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz; in intel_ring_default_vfuncs()
2178 engine->emit_breadcrumb = gen6_sema_emit_breadcrumb; in intel_ring_default_vfuncs()
2181 engine->emit_breadcrumb_sz += num_rings * 3; in intel_ring_default_vfuncs()
2183 engine->emit_breadcrumb_sz++; in intel_ring_default_vfuncs()
2186 engine->set_default_submission = i9xx_set_default_submission; in intel_ring_default_vfuncs()
2189 engine->emit_bb_start = gen6_emit_bb_start; in intel_ring_default_vfuncs()
2191 engine->emit_bb_start = i965_emit_bb_start; in intel_ring_default_vfuncs()
2193 engine->emit_bb_start = i830_emit_bb_start; in intel_ring_default_vfuncs()
2195 engine->emit_bb_start = i915_emit_bb_start; in intel_ring_default_vfuncs()
2198 int intel_init_render_ring_buffer(struct intel_engine_cs *engine) in intel_init_render_ring_buffer() argument
2200 struct drm_i915_private *dev_priv = engine->i915; in intel_init_render_ring_buffer()
2203 intel_ring_default_vfuncs(dev_priv, engine); in intel_init_render_ring_buffer()
2206 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; in intel_init_render_ring_buffer()
2208 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; in intel_init_render_ring_buffer()
2211 engine->init_context = intel_rcs_ctx_init; in intel_init_render_ring_buffer()
2212 engine->emit_flush = gen7_render_ring_flush; in intel_init_render_ring_buffer()
2214 engine->emit_flush = gen6_render_ring_flush; in intel_init_render_ring_buffer()
2216 engine->emit_flush = gen4_render_ring_flush; in intel_init_render_ring_buffer()
2219 engine->emit_flush = gen2_render_ring_flush; in intel_init_render_ring_buffer()
2221 engine->emit_flush = gen4_render_ring_flush; in intel_init_render_ring_buffer()
2222 engine->irq_enable_mask = I915_USER_INTERRUPT; in intel_init_render_ring_buffer()
2226 engine->emit_bb_start = hsw_emit_bb_start; in intel_init_render_ring_buffer()
2228 engine->init_hw = init_render_ring; in intel_init_render_ring_buffer()
2230 ret = intel_init_ring_buffer(engine); in intel_init_render_ring_buffer()
2237 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) in intel_init_bsd_ring_buffer() argument
2239 struct drm_i915_private *dev_priv = engine->i915; in intel_init_bsd_ring_buffer()
2241 intel_ring_default_vfuncs(dev_priv, engine); in intel_init_bsd_ring_buffer()
2246 engine->set_default_submission = gen6_bsd_set_default_submission; in intel_init_bsd_ring_buffer()
2247 engine->emit_flush = gen6_bsd_ring_flush; in intel_init_bsd_ring_buffer()
2248 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; in intel_init_bsd_ring_buffer()
2250 engine->emit_flush = bsd_ring_flush; in intel_init_bsd_ring_buffer()
2252 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; in intel_init_bsd_ring_buffer()
2254 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; in intel_init_bsd_ring_buffer()
2257 return intel_init_ring_buffer(engine); in intel_init_bsd_ring_buffer()
2260 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) in intel_init_blt_ring_buffer() argument
2262 struct drm_i915_private *dev_priv = engine->i915; in intel_init_blt_ring_buffer()
2264 intel_ring_default_vfuncs(dev_priv, engine); in intel_init_blt_ring_buffer()
2266 engine->emit_flush = gen6_ring_flush; in intel_init_blt_ring_buffer()
2267 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; in intel_init_blt_ring_buffer()
2269 return intel_init_ring_buffer(engine); in intel_init_blt_ring_buffer()
2272 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) in intel_init_vebox_ring_buffer() argument
2274 struct drm_i915_private *dev_priv = engine->i915; in intel_init_vebox_ring_buffer()
2276 intel_ring_default_vfuncs(dev_priv, engine); in intel_init_vebox_ring_buffer()
2278 engine->emit_flush = gen6_ring_flush; in intel_init_vebox_ring_buffer()
2279 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; in intel_init_vebox_ring_buffer()
2280 engine->irq_enable = hsw_vebox_irq_enable; in intel_init_vebox_ring_buffer()
2281 engine->irq_disable = hsw_vebox_irq_disable; in intel_init_vebox_ring_buffer()
2283 return intel_init_ring_buffer(engine); in intel_init_vebox_ring_buffer()