59 void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug)  in intel_psr_irq_control()  argument
67 	if (INTEL_GEN(dev_priv) >= 8) {  in intel_psr_irq_control()
83 	WRITE_ONCE(dev_priv->psr.debug, debug);  in intel_psr_irq_control()
124 void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir)  in intel_psr_irq_handler()  argument
130 	if (INTEL_GEN(dev_priv) >= 8)  in intel_psr_irq_handler()
135 	for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {  in intel_psr_irq_handler()
142 			dev_priv->psr.last_entry_attempt = time_ns;  in intel_psr_irq_handler()
148 			dev_priv->psr.last_exit = time_ns;  in intel_psr_irq_handler()
152 			if (INTEL_GEN(dev_priv) >= 9) {  in intel_psr_irq_handler()
154 				bool psr2_enabled = dev_priv->psr.psr2_enabled;  in intel_psr_irq_handler()
197 	struct drm_i915_private *dev_priv =  in intel_psr_init_dpcd()  local
212 	dev_priv->psr.sink_support = true;  in intel_psr_init_dpcd()
213 	dev_priv->psr.sink_sync_latency =  in intel_psr_init_dpcd()
216 	if (INTEL_GEN(dev_priv) >= 9 &&  in intel_psr_init_dpcd()
233 		dev_priv->psr.sink_psr2_support = y_req && alpm;  in intel_psr_init_dpcd()
235 			      dev_priv->psr.sink_psr2_support ? "" : "not ");  in intel_psr_init_dpcd()
237 		if (dev_priv->psr.sink_psr2_support) {  in intel_psr_init_dpcd()
238 			dev_priv->psr.colorimetry_support =  in intel_psr_init_dpcd()
248 	struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);  in intel_psr_setup_vsc()  local
251 	if (dev_priv->psr.psr2_enabled) {  in intel_psr_setup_vsc()
256 		if (dev_priv->psr.colorimetry_support) {  in intel_psr_setup_vsc()
279 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);  in hsw_psr_setup_aux()  local
314 	struct drm_i915_private *dev_priv = to_i915(dev);  in intel_psr_enable_sink()  local
318 	if (dev_priv->psr.psr2_enabled) {  in intel_psr_enable_sink()
324 	if (dev_priv->psr.link_standby)  in intel_psr_enable_sink()
326 	if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >= 8)  in intel_psr_enable_sink()
337 	struct drm_i915_private *dev_priv = to_i915(dev);  in hsw_activate_psr1()  local
344 	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);  in hsw_activate_psr1()
349 	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);  in hsw_activate_psr1()
353 	if (IS_HASWELL(dev_priv))  in hsw_activate_psr1()
356 	if (dev_priv->psr.link_standby)  in hsw_activate_psr1()
359 	if (dev_priv->vbt.psr.tp1_wakeup_time_us == 0)  in hsw_activate_psr1()
361 	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 100)  in hsw_activate_psr1()
363 	else if (dev_priv->vbt.psr.tp1_wakeup_time_us <= 500)  in hsw_activate_psr1()
368 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us == 0)  in hsw_activate_psr1()
370 	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)  in hsw_activate_psr1()
372 	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)  in hsw_activate_psr1()
383 	if (INTEL_GEN(dev_priv) >= 8)  in hsw_activate_psr1()
394 	struct drm_i915_private *dev_priv = to_i915(dev);  in hsw_activate_psr2()  local
400 	int idle_frames = max(6, dev_priv->vbt.psr.idle_frames);  in hsw_activate_psr2()
402 	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);  in hsw_activate_psr2()
409 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))  in hsw_activate_psr2()
412 	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);  in hsw_activate_psr2()
414 	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us >= 0 &&  in hsw_activate_psr2()
415 	    dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 50)  in hsw_activate_psr2()
417 	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 100)  in hsw_activate_psr2()
419 	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time_us <= 500)  in hsw_activate_psr2()
431 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);  in intel_psr2_config_valid()  local
441 	if (!dev_priv->psr.sink_psr2_support)  in intel_psr2_config_valid()
444 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {  in intel_psr2_config_valid()
447 	} else if (IS_GEN9(dev_priv)) {  in intel_psr2_config_valid()
466 	struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);  in intel_psr_compute_config()  local
471 	if (!CAN_PSR(dev_priv))  in intel_psr_compute_config()
491 	if (IS_HASWELL(dev_priv) &&  in intel_psr_compute_config()
498 	if (IS_HASWELL(dev_priv) &&  in intel_psr_compute_config()
527 	struct drm_i915_private *dev_priv = to_i915(dev);  in intel_psr_activate()  local
529 	if (INTEL_GEN(dev_priv) >= 9)  in intel_psr_activate()
532 	WARN_ON(dev_priv->psr.active);  in intel_psr_activate()
533 	lockdep_assert_held(&dev_priv->psr.lock);  in intel_psr_activate()
536 	if (dev_priv->psr.psr2_enabled)  in intel_psr_activate()
541 	dev_priv->psr.active = true;  in intel_psr_activate()
549 	struct drm_i915_private *dev_priv = to_i915(dev);  in intel_psr_enable_source()  local
555 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))  in intel_psr_enable_source()
558 	if (dev_priv->psr.psr2_enabled) {  in intel_psr_enable_source()
561 		if (INTEL_GEN(dev_priv) == 9 && !IS_GEMINILAKE(dev_priv))  in intel_psr_enable_source()
604 	struct drm_i915_private *dev_priv = to_i915(dev);  in intel_psr_enable()  local
609 	if (WARN_ON(!CAN_PSR(dev_priv)))  in intel_psr_enable()
612 	WARN_ON(dev_priv->drrs.dp);  in intel_psr_enable()
613 	mutex_lock(&dev_priv->psr.lock);  in intel_psr_enable()
614 	if (dev_priv->psr.enabled) {  in intel_psr_enable()
619 	dev_priv->psr.psr2_enabled = crtc_state->has_psr2;  in intel_psr_enable()
620 	dev_priv->psr.busy_frontbuffer_bits = 0;  in intel_psr_enable()
625 	dev_priv->psr.enabled = intel_dp;  in intel_psr_enable()
630 	mutex_unlock(&dev_priv->psr.lock);  in intel_psr_enable()
638 	struct drm_i915_private *dev_priv = to_i915(dev);  in intel_psr_disable_source()  local
640 	if (dev_priv->psr.active) {  in intel_psr_disable_source()
644 		if (dev_priv->psr.psr2_enabled) {  in intel_psr_disable_source()
661 		if (intel_wait_for_register(dev_priv,  in intel_psr_disable_source()
666 		dev_priv->psr.active = false;  in intel_psr_disable_source()
668 		if (dev_priv->psr.psr2_enabled)  in intel_psr_disable_source()
679 	struct drm_i915_private *dev_priv = to_i915(dev);  in intel_psr_disable_locked()  local
681 	lockdep_assert_held(&dev_priv->psr.lock);  in intel_psr_disable_locked()
683 	if (!dev_priv->psr.enabled)  in intel_psr_disable_locked()
691 	dev_priv->psr.enabled = NULL;  in intel_psr_disable_locked()
706 	struct drm_i915_private *dev_priv = to_i915(dev);  in intel_psr_disable()  local
711 	if (WARN_ON(!CAN_PSR(dev_priv)))  in intel_psr_disable()
714 	mutex_lock(&dev_priv->psr.lock);  in intel_psr_disable()
716 	mutex_unlock(&dev_priv->psr.lock);  in intel_psr_disable()
717 	cancel_work_sync(&dev_priv->psr.work);  in intel_psr_disable()
723 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in intel_psr_wait_for_idle()  local
740 	if (dev_priv->psr.psr2_enabled) {  in intel_psr_wait_for_idle()
753 	return intel_wait_for_register(dev_priv, reg, mask,  in intel_psr_wait_for_idle()
757 static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv)  in __psr_wait_for_idle_locked()  argument
764 	intel_dp = dev_priv->psr.enabled;  in __psr_wait_for_idle_locked()
768 	if (dev_priv->psr.psr2_enabled) {  in __psr_wait_for_idle_locked()
776 	mutex_unlock(&dev_priv->psr.lock);  in __psr_wait_for_idle_locked()
778 	err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);  in __psr_wait_for_idle_locked()
783 	mutex_lock(&dev_priv->psr.lock);  in __psr_wait_for_idle_locked()
784 	return err == 0 && dev_priv->psr.enabled;  in __psr_wait_for_idle_locked()
789 	struct drm_i915_private *dev_priv =  in intel_psr_work()  local
790 		container_of(work, typeof(*dev_priv), psr.work);  in intel_psr_work()
792 	mutex_lock(&dev_priv->psr.lock);  in intel_psr_work()
794 	if (!dev_priv->psr.enabled)  in intel_psr_work()
803 	if (!__psr_wait_for_idle_locked(dev_priv))  in intel_psr_work()
811 	if (dev_priv->psr.busy_frontbuffer_bits || dev_priv->psr.active)  in intel_psr_work()
814 	intel_psr_activate(dev_priv->psr.enabled);  in intel_psr_work()
816 	mutex_unlock(&dev_priv->psr.lock);  in intel_psr_work()
819 static void intel_psr_exit(struct drm_i915_private *dev_priv)  in intel_psr_exit()  argument
823 	if (!dev_priv->psr.active)  in intel_psr_exit()
826 	if (dev_priv->psr.psr2_enabled) {  in intel_psr_exit()
835 	dev_priv->psr.active = false;  in intel_psr_exit()
851 void intel_psr_invalidate(struct drm_i915_private *dev_priv,  in intel_psr_invalidate()  argument
857 	if (!CAN_PSR(dev_priv))  in intel_psr_invalidate()
863 	mutex_lock(&dev_priv->psr.lock);  in intel_psr_invalidate()
864 	if (!dev_priv->psr.enabled) {  in intel_psr_invalidate()
865 		mutex_unlock(&dev_priv->psr.lock);  in intel_psr_invalidate()
869 	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;  in intel_psr_invalidate()
873 	dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;  in intel_psr_invalidate()
876 		intel_psr_exit(dev_priv);  in intel_psr_invalidate()
878 	mutex_unlock(&dev_priv->psr.lock);  in intel_psr_invalidate()
894 void intel_psr_flush(struct drm_i915_private *dev_priv,  in intel_psr_flush()  argument
900 	if (!CAN_PSR(dev_priv))  in intel_psr_flush()
906 	mutex_lock(&dev_priv->psr.lock);  in intel_psr_flush()
907 	if (!dev_priv->psr.enabled) {  in intel_psr_flush()
908 		mutex_unlock(&dev_priv->psr.lock);  in intel_psr_flush()
912 	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;  in intel_psr_flush()
916 	dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;  in intel_psr_flush()
920 		if (dev_priv->psr.psr2_enabled) {  in intel_psr_flush()
921 			intel_psr_exit(dev_priv);  in intel_psr_flush()
936 	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)  in intel_psr_flush()
937 		schedule_work(&dev_priv->psr.work);  in intel_psr_flush()
938 	mutex_unlock(&dev_priv->psr.lock);  in intel_psr_flush()
948 void intel_psr_init(struct drm_i915_private *dev_priv)  in intel_psr_init()  argument
950 	if (!HAS_PSR(dev_priv))  in intel_psr_init()
953 	dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?  in intel_psr_init()
956 	if (!dev_priv->psr.sink_support)  in intel_psr_init()
960 		i915_modparams.enable_psr = dev_priv->vbt.psr.enable;  in intel_psr_init()
967 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))  in intel_psr_init()
969 		dev_priv->psr.link_standby = false;  in intel_psr_init()
972 		dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;  in intel_psr_init()
974 	INIT_WORK(&dev_priv->psr.work, intel_psr_work);  in intel_psr_init()
975 	mutex_init(&dev_priv->psr.lock);  in intel_psr_init()
982 	struct drm_i915_private *dev_priv = to_i915(dev);  in intel_psr_short_pulse()  local
983 	struct i915_psr *psr = &dev_priv->psr;  in intel_psr_short_pulse()
989 	if (!CAN_PSR(dev_priv) || !intel_dp_is_edp(intel_dp))  in intel_psr_short_pulse()