89 	DRM_DEBUG_KMS("PSR exit events: 0x%x\n", val);  in psr_event_print()
91 		DRM_DEBUG_KMS("\tPSR2 watchdog timer expired\n");  in psr_event_print()
93 		DRM_DEBUG_KMS("\tPSR2 disabled\n");  in psr_event_print()
95 		DRM_DEBUG_KMS("\tSU dirty FIFO underrun\n");  in psr_event_print()
97 		DRM_DEBUG_KMS("\tSU CRC FIFO underrun\n");  in psr_event_print()
99 		DRM_DEBUG_KMS("\tGraphics reset\n");  in psr_event_print()
101 		DRM_DEBUG_KMS("\tPCH interrupt\n");  in psr_event_print()
103 		DRM_DEBUG_KMS("\tMemory up\n");  in psr_event_print()
105 		DRM_DEBUG_KMS("\tFront buffer modification\n");  in psr_event_print()
107 		DRM_DEBUG_KMS("\tPSR watchdog timer expired\n");  in psr_event_print()
109 		DRM_DEBUG_KMS("\tPIPE registers updated\n");  in psr_event_print()
111 		DRM_DEBUG_KMS("\tRegister updated\n");  in psr_event_print()
113 		DRM_DEBUG_KMS("\tHDCP enabled\n");  in psr_event_print()
115 		DRM_DEBUG_KMS("\tKVMR session enabled\n");  in psr_event_print()
117 		DRM_DEBUG_KMS("\tVBI enabled\n");  in psr_event_print()
119 		DRM_DEBUG_KMS("\tLPSP mode exited\n");  in psr_event_print()
121 		DRM_DEBUG_KMS("\tPSR disabled\n");  in psr_event_print()
138 			DRM_DEBUG_KMS("[transcoder %s] PSR aux error\n",  in intel_psr_irq_handler()
143 			DRM_DEBUG_KMS("[transcoder %s] PSR entry attempt in 2 vblanks\n",  in intel_psr_irq_handler()
149 			DRM_DEBUG_KMS("[transcoder %s] PSR exit completed\n",  in intel_psr_irq_handler()
191 		DRM_DEBUG_KMS("Unable to get sink synchronization latency, assuming 8 frames\n");  in intel_dp_get_sink_sync_latency()
205 	DRM_DEBUG_KMS("eDP panel supports PSR version %x\n",  in intel_psr_init_dpcd()
209 		DRM_DEBUG_KMS("Panel lacks power state control, PSR cannot be enabled\n");  in intel_psr_init_dpcd()
234 		DRM_DEBUG_KMS("PSR2 %ssupported\n",  in intel_psr_init_dpcd()
453 		DRM_DEBUG_KMS("PSR2 not enabled, resolution %dx%d > max supported %dx%d\n",  in intel_psr2_config_valid()
475 		DRM_DEBUG_KMS("PSR disable by flag\n");  in intel_psr_compute_config()
487 		DRM_DEBUG_KMS("PSR condition failed: Port not supported\n");  in intel_psr_compute_config()
494 		DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");  in intel_psr_compute_config()
500 		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");  in intel_psr_compute_config()
506 		DRM_DEBUG_KMS("PSR condition failed: Invalid PSR setup time (0x%02x)\n",  in intel_psr_compute_config()
513 		DRM_DEBUG_KMS("PSR condition failed: PSR setup time (%d us) too long\n",  in intel_psr_compute_config()
520 	DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : "");  in intel_psr_compute_config()
615 		DRM_DEBUG_KMS("PSR already in use\n");  in intel_psr_enable()
1003 		DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");  in intel_psr_short_pulse()
1013 		DRM_DEBUG_KMS("PSR RFB storage error, disabling PSR\n");  in intel_psr_short_pulse()
1015 		DRM_DEBUG_KMS("PSR VSC SDP uncorrectable error, disabling PSR\n");  in intel_psr_short_pulse()