Lines Matching refs:wm
443 mutex_lock(&dev_priv->wm.wm_mutex); in intel_set_memory_cxsr()
446 dev_priv->wm.vlv.cxsr = enable; in intel_set_memory_cxsr()
448 dev_priv->wm.g4x.cxsr = enable; in intel_set_memory_cxsr()
449 mutex_unlock(&dev_priv->wm.wm_mutex); in intel_set_memory_cxsr()
477 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_get_fifo_size()
748 const struct intel_watermark_params *wm, in intel_calculate_wm() argument
762 entries = DIV_ROUND_UP(entries, wm->cacheline_size) + in intel_calculate_wm()
763 wm->guard_size; in intel_calculate_wm()
770 if (wm_size > wm->max_wm) in intel_calculate_wm()
771 wm_size = wm->max_wm; in intel_calculate_wm()
773 wm_size = wm->default_wm; in intel_calculate_wm()
800 return dev_priv->wm.max_level + 1; in intel_wm_num_levels()
847 unsigned int wm; in pineview_update_wm() local
869 wm = intel_calculate_wm(clock, &pineview_display_wm, in pineview_update_wm()
874 reg |= FW_WM(wm, SR); in pineview_update_wm()
879 wm = intel_calculate_wm(clock, &pineview_cursor_wm, in pineview_update_wm()
884 reg |= FW_WM(wm, CURSOR_SR); in pineview_update_wm()
888 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, in pineview_update_wm()
893 reg |= FW_WM(wm, HPLL_SR); in pineview_update_wm()
897 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, in pineview_update_wm()
902 reg |= FW_WM(wm, HPLL_CURSOR); in pineview_update_wm()
930 const struct g4x_wm_values *wm) in g4x_write_wm_values() argument
935 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm); in g4x_write_wm_values()
938 FW_WM(wm->sr.plane, SR) | in g4x_write_wm_values()
939 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in g4x_write_wm_values()
940 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in g4x_write_wm_values()
941 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
943 (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) | in g4x_write_wm_values()
944 FW_WM(wm->sr.fbc, FBC_SR) | in g4x_write_wm_values()
945 FW_WM(wm->hpll.fbc, FBC_HPLL_SR) | in g4x_write_wm_values()
946 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | in g4x_write_wm_values()
947 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in g4x_write_wm_values()
948 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in g4x_write_wm_values()
950 (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) | in g4x_write_wm_values()
951 FW_WM(wm->sr.cursor, CURSOR_SR) | in g4x_write_wm_values()
952 FW_WM(wm->hpll.cursor, HPLL_CURSOR) | in g4x_write_wm_values()
953 FW_WM(wm->hpll.plane, HPLL_SR)); in g4x_write_wm_values()
962 const struct vlv_wm_values *wm) in vlv_write_wm_values() argument
967 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm); in vlv_write_wm_values()
970 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) | in vlv_write_wm_values()
971 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) | in vlv_write_wm_values()
972 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) | in vlv_write_wm_values()
973 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT)); in vlv_write_wm_values()
988 FW_WM(wm->sr.plane, SR) | in vlv_write_wm_values()
989 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in vlv_write_wm_values()
990 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in vlv_write_wm_values()
991 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in vlv_write_wm_values()
993 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | in vlv_write_wm_values()
994 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in vlv_write_wm_values()
995 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in vlv_write_wm_values()
997 FW_WM(wm->sr.cursor, CURSOR_SR)); in vlv_write_wm_values()
1001 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | in vlv_write_wm_values()
1002 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); in vlv_write_wm_values()
1004 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) | in vlv_write_wm_values()
1005 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE)); in vlv_write_wm_values()
1007 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) | in vlv_write_wm_values()
1008 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC)); in vlv_write_wm_values()
1010 FW_WM(wm->sr.plane >> 9, SR_HI) | in vlv_write_wm_values()
1011 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) | in vlv_write_wm_values()
1012 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) | in vlv_write_wm_values()
1013 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) | in vlv_write_wm_values()
1014 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
1015 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
1016 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | in vlv_write_wm_values()
1017 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
1018 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
1019 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); in vlv_write_wm_values()
1022 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | in vlv_write_wm_values()
1023 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); in vlv_write_wm_values()
1025 FW_WM(wm->sr.plane >> 9, SR_HI) | in vlv_write_wm_values()
1026 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
1027 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
1028 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | in vlv_write_wm_values()
1029 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | in vlv_write_wm_values()
1030 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | in vlv_write_wm_values()
1031 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); in vlv_write_wm_values()
1042 dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5; in g4x_setup_wm_latency()
1043 dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12; in g4x_setup_wm_latency()
1044 dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35; in g4x_setup_wm_latency()
1046 dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL; in g4x_setup_wm_latency()
1099 unsigned int latency = dev_priv->wm.pri_latency[level] * 10; in g4x_compute_wm()
1100 unsigned int clock, htotal, cpp, width, wm; in g4x_compute_wm() local
1134 wm = intel_wm_method2(clock, htotal, width, cpp, latency); in g4x_compute_wm()
1137 wm = intel_wm_method1(clock, cpp, latency); in g4x_compute_wm()
1144 wm = min(small, large); in g4x_compute_wm()
1147 wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level), in g4x_compute_wm()
1150 wm = DIV_ROUND_UP(wm, 64) + 2; in g4x_compute_wm()
1152 return min_t(unsigned int, wm, USHRT_MAX); in g4x_compute_wm()
1162 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_set()
1181 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_fbc_wm_set()
1211 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_compute()
1212 int wm, max_wm; in g4x_raw_plane_wm_compute() local
1214 wm = g4x_compute_wm(crtc_state, plane_state, level); in g4x_raw_plane_wm_compute()
1217 if (wm > max_wm) in g4x_raw_plane_wm_compute()
1220 dirty |= raw->plane[plane_id] != wm; in g4x_raw_plane_wm_compute()
1221 raw->plane[plane_id] = wm; in g4x_raw_plane_wm_compute()
1227 wm = ilk_compute_fbc_wm(crtc_state, plane_state, in g4x_raw_plane_wm_compute()
1235 if (wm > max_wm) in g4x_raw_plane_wm_compute()
1236 wm = USHRT_MAX; in g4x_raw_plane_wm_compute()
1238 dirty |= raw->fbc != wm; in g4x_raw_plane_wm_compute()
1239 raw->fbc = wm; in g4x_raw_plane_wm_compute()
1252 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id], in g4x_raw_plane_wm_compute()
1253 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id], in g4x_raw_plane_wm_compute()
1254 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]); in g4x_raw_plane_wm_compute()
1258 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc, in g4x_raw_plane_wm_compute()
1259 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc); in g4x_raw_plane_wm_compute()
1268 const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; in g4x_raw_plane_wm_is_valid()
1278 if (level > dev_priv->wm.max_level) in g4x_raw_crtc_wm_is_valid()
1294 wm_state->wm.plane[plane_id] = USHRT_MAX; in g4x_invalidate_wms()
1317 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; in g4x_compute_pipe_wm()
1346 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1348 wm_state->wm.plane[plane_id] = raw->plane[plane_id]; in g4x_compute_pipe_wm()
1355 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1367 raw = &crtc_state->wm.g4x.raw[level]; in g4x_compute_pipe_wm()
1405 struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate; in g4x_compute_intermediate_wm()
1406 const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal; in g4x_compute_intermediate_wm()
1411 const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal; in g4x_compute_intermediate_wm()
1429 intermediate->wm.plane[plane_id] = in g4x_compute_intermediate_wm()
1430 max(optimal->wm.plane[plane_id], in g4x_compute_intermediate_wm()
1431 active->wm.plane[plane_id]); in g4x_compute_intermediate_wm()
1433 WARN_ON(intermediate->wm.plane[plane_id] > in g4x_compute_intermediate_wm()
1473 new_crtc_state->wm.need_postvbl_update = true; in g4x_compute_intermediate_wm()
1479 struct g4x_wm_values *wm) in g4x_merge_wm() argument
1484 wm->cxsr = true; in g4x_merge_wm()
1485 wm->hpll_en = true; in g4x_merge_wm()
1486 wm->fbc_en = true; in g4x_merge_wm()
1489 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; in g4x_merge_wm()
1495 wm->cxsr = false; in g4x_merge_wm()
1497 wm->hpll_en = false; in g4x_merge_wm()
1499 wm->fbc_en = false; in g4x_merge_wm()
1505 wm->cxsr = false; in g4x_merge_wm()
1506 wm->hpll_en = false; in g4x_merge_wm()
1507 wm->fbc_en = false; in g4x_merge_wm()
1511 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; in g4x_merge_wm()
1514 wm->pipe[pipe] = wm_state->wm; in g4x_merge_wm()
1515 if (crtc->active && wm->cxsr) in g4x_merge_wm()
1516 wm->sr = wm_state->sr; in g4x_merge_wm()
1517 if (crtc->active && wm->hpll_en) in g4x_merge_wm()
1518 wm->hpll = wm_state->hpll; in g4x_merge_wm()
1524 struct g4x_wm_values *old_wm = &dev_priv->wm.g4x; in g4x_program_watermarks()
1549 mutex_lock(&dev_priv->wm.wm_mutex); in g4x_initial_watermarks()
1550 crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate; in g4x_initial_watermarks()
1552 mutex_unlock(&dev_priv->wm.wm_mutex); in g4x_initial_watermarks()
1561 if (!crtc_state->wm.need_postvbl_update) in g4x_optimize_watermarks()
1564 mutex_lock(&dev_priv->wm.wm_mutex); in g4x_optimize_watermarks()
1565 intel_crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; in g4x_optimize_watermarks()
1567 mutex_unlock(&dev_priv->wm.wm_mutex); in g4x_optimize_watermarks()
1589 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; in vlv_setup_wm_latency()
1591 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; in vlv_setup_wm_latency()
1594 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; in vlv_setup_wm_latency()
1595 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; in vlv_setup_wm_latency()
1597 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; in vlv_setup_wm_latency()
1609 unsigned int clock, htotal, cpp, width, wm; in vlv_compute_wm_level() local
1611 if (dev_priv->wm.pri_latency[level] == 0) in vlv_compute_wm_level()
1629 wm = 63; in vlv_compute_wm_level()
1631 wm = vlv_wm_method2(clock, htotal, width, cpp, in vlv_compute_wm_level()
1632 dev_priv->wm.pri_latency[level] * 10); in vlv_compute_wm_level()
1635 return min_t(unsigned int, wm, USHRT_MAX); in vlv_compute_wm_level()
1648 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2]; in vlv_compute_fifo()
1649 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; in vlv_compute_fifo()
1736 wm_state->wm[level].plane[plane_id] = USHRT_MAX; in vlv_invalidate_wms()
1743 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size) in vlv_invert_wm_value() argument
1745 if (wm > fifo_size) in vlv_invert_wm_value()
1748 return fifo_size - wm; in vlv_invert_wm_value()
1763 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_set()
1787 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_compute()
1788 int wm = vlv_compute_wm_level(crtc_state, plane_state, level); in vlv_raw_plane_wm_compute() local
1791 if (wm > max_wm) in vlv_raw_plane_wm_compute()
1794 dirty |= raw->plane[plane_id] != wm; in vlv_raw_plane_wm_compute()
1795 raw->plane[plane_id] = wm; in vlv_raw_plane_wm_compute()
1805 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], in vlv_raw_plane_wm_compute()
1806 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], in vlv_raw_plane_wm_compute()
1807 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); in vlv_raw_plane_wm_compute()
1816 &crtc_state->wm.vlv.raw[level]; in vlv_raw_plane_wm_is_valid()
1818 &crtc_state->wm.vlv.fifo_state; in vlv_raw_plane_wm_is_valid()
1837 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; in vlv_compute_pipe_wm()
1839 &crtc_state->wm.vlv.fifo_state; in vlv_compute_pipe_wm()
1878 &old_crtc_state->wm.vlv.fifo_state; in vlv_compute_pipe_wm()
1900 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; in vlv_compute_pipe_wm()
1907 wm_state->wm[level].plane[plane_id] = in vlv_compute_pipe_wm()
1944 &crtc_state->wm.vlv.fifo_state; in vlv_atomic_update_fifo()
2038 struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate; in vlv_compute_intermediate_wm()
2039 const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal; in vlv_compute_intermediate_wm()
2044 const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal; in vlv_compute_intermediate_wm()
2062 intermediate->wm[level].plane[plane_id] = in vlv_compute_intermediate_wm()
2063 min(optimal->wm[level].plane[plane_id], in vlv_compute_intermediate_wm()
2064 active->wm[level].plane[plane_id]); in vlv_compute_intermediate_wm()
2081 new_crtc_state->wm.need_postvbl_update = true; in vlv_compute_intermediate_wm()
2087 struct vlv_wm_values *wm) in vlv_merge_wm() argument
2092 wm->level = dev_priv->wm.max_level; in vlv_merge_wm()
2093 wm->cxsr = true; in vlv_merge_wm()
2096 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; in vlv_merge_wm()
2102 wm->cxsr = false; in vlv_merge_wm()
2105 wm->level = min_t(int, wm->level, wm_state->num_levels - 1); in vlv_merge_wm()
2109 wm->cxsr = false; in vlv_merge_wm()
2112 wm->level = VLV_WM_LEVEL_PM2; in vlv_merge_wm()
2115 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; in vlv_merge_wm()
2118 wm->pipe[pipe] = wm_state->wm[wm->level]; in vlv_merge_wm()
2119 if (crtc->active && wm->cxsr) in vlv_merge_wm()
2120 wm->sr = wm_state->sr[wm->level]; in vlv_merge_wm()
2122 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
2123 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
2124 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
2125 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2; in vlv_merge_wm()
2131 struct vlv_wm_values *old_wm = &dev_priv->wm.vlv; in vlv_program_watermarks()
2168 mutex_lock(&dev_priv->wm.wm_mutex); in vlv_initial_watermarks()
2169 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate; in vlv_initial_watermarks()
2171 mutex_unlock(&dev_priv->wm.wm_mutex); in vlv_initial_watermarks()
2180 if (!crtc_state->wm.need_postvbl_update) in vlv_optimize_watermarks()
2183 mutex_lock(&dev_priv->wm.wm_mutex); in vlv_optimize_watermarks()
2184 intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; in vlv_optimize_watermarks()
2186 mutex_unlock(&dev_priv->wm.wm_mutex); in vlv_optimize_watermarks()
2745 uint16_t pri_latency = dev_priv->wm.pri_latency[level]; in ilk_compute_wm_level()
2746 uint16_t spr_latency = dev_priv->wm.spr_latency[level]; in ilk_compute_wm_level()
2747 uint16_t cur_latency = dev_priv->wm.cur_latency[level]; in ilk_compute_wm_level()
2800 uint16_t wm[8]) in intel_read_wm_latency()
2820 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; in intel_read_wm_latency()
2821 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & in intel_read_wm_latency()
2823 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & in intel_read_wm_latency()
2825 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & in intel_read_wm_latency()
2840 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; in intel_read_wm_latency()
2841 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & in intel_read_wm_latency()
2843 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & in intel_read_wm_latency()
2845 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & in intel_read_wm_latency()
2854 if (wm[level] == 0) { in intel_read_wm_latency()
2856 wm[i] = 0; in intel_read_wm_latency()
2868 if (wm[0] == 0) { in intel_read_wm_latency()
2869 wm[0] += 2; in intel_read_wm_latency()
2871 if (wm[level] == 0) in intel_read_wm_latency()
2873 wm[level] += 2; in intel_read_wm_latency()
2880 wm[0] = (sskpd >> 56) & 0xFF; in intel_read_wm_latency()
2881 if (wm[0] == 0) in intel_read_wm_latency()
2882 wm[0] = sskpd & 0xF; in intel_read_wm_latency()
2883 wm[1] = (sskpd >> 4) & 0xFF; in intel_read_wm_latency()
2884 wm[2] = (sskpd >> 12) & 0xFF; in intel_read_wm_latency()
2885 wm[3] = (sskpd >> 20) & 0x1FF; in intel_read_wm_latency()
2886 wm[4] = (sskpd >> 32) & 0x1FF; in intel_read_wm_latency()
2890 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; in intel_read_wm_latency()
2891 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; in intel_read_wm_latency()
2892 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; in intel_read_wm_latency()
2893 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; in intel_read_wm_latency()
2898 wm[0] = 7; in intel_read_wm_latency()
2899 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; in intel_read_wm_latency()
2900 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; in intel_read_wm_latency()
2907 uint16_t wm[5]) in intel_fixup_spr_wm_latency()
2911 wm[0] = 13; in intel_fixup_spr_wm_latency()
2915 uint16_t wm[5]) in intel_fixup_cur_wm_latency()
2919 wm[0] = 13; in intel_fixup_cur_wm_latency()
2937 const uint16_t wm[8]) in intel_print_wm_latency()
2942 unsigned int latency = wm[level]; in intel_print_wm_latency()
2960 name, level, wm[level], in intel_print_wm_latency()
2966 uint16_t wm[5], uint16_t min) in ilk_increase_wm_latency()
2970 if (wm[0] >= min) in ilk_increase_wm_latency()
2973 wm[0] = max(wm[0], min); in ilk_increase_wm_latency()
2975 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); in ilk_increase_wm_latency()
2988 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | in snb_wm_latency_quirk()
2989 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | in snb_wm_latency_quirk()
2990 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); in snb_wm_latency_quirk()
2996 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); in snb_wm_latency_quirk()
2997 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); in snb_wm_latency_quirk()
2998 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); in snb_wm_latency_quirk()
3003 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency); in ilk_setup_wm_latency()
3005 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, in ilk_setup_wm_latency()
3006 sizeof(dev_priv->wm.pri_latency)); in ilk_setup_wm_latency()
3007 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, in ilk_setup_wm_latency()
3008 sizeof(dev_priv->wm.pri_latency)); in ilk_setup_wm_latency()
3010 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency); in ilk_setup_wm_latency()
3011 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency); in ilk_setup_wm_latency()
3013 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); in ilk_setup_wm_latency()
3014 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); in ilk_setup_wm_latency()
3015 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); in ilk_setup_wm_latency()
3023 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency); in skl_setup_wm_latency()
3024 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency); in skl_setup_wm_latency()
3042 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) { in ilk_validate_pipe_wm()
3066 pipe_wm = &cstate->wm.ilk.optimal; in ilk_compute_pipe_wm()
3097 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm)); in ilk_compute_pipe_wm()
3099 pristate, sprstate, curstate, &pipe_wm->wm[0]); in ilk_compute_pipe_wm()
3110 struct intel_wm_level *wm = &pipe_wm->wm[level]; in ilk_compute_pipe_wm() local
3113 pristate, sprstate, curstate, wm); in ilk_compute_pipe_wm()
3120 if (!ilk_validate_wm_level(level, &max, wm)) { in ilk_compute_pipe_wm()
3121 memset(wm, 0, sizeof(*wm)); in ilk_compute_pipe_wm()
3138 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate; in ilk_compute_intermediate_wm()
3143 const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal; in ilk_compute_intermediate_wm()
3151 *a = newstate->wm.ilk.optimal; in ilk_compute_intermediate_wm()
3160 struct intel_wm_level *a_wm = &a->wm[level]; in ilk_compute_intermediate_wm()
3161 const struct intel_wm_level *b_wm = &b->wm[level]; in ilk_compute_intermediate_wm()
3183 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0) in ilk_compute_intermediate_wm()
3184 newstate->wm.need_postvbl_update = true; in ilk_compute_intermediate_wm()
3201 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk; in ilk_merge_wm_level()
3202 const struct intel_wm_level *wm = &active->wm[level]; in ilk_merge_wm_level() local
3212 if (!wm->enable) in ilk_merge_wm_level()
3215 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); in ilk_merge_wm_level()
3216 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); in ilk_merge_wm_level()
3217 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); in ilk_merge_wm_level()
3218 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); in ilk_merge_wm_level()
3244 struct intel_wm_level *wm = &merged->wm[level]; in ilk_wm_merge() local
3246 ilk_merge_wm_level(dev, level, wm); in ilk_wm_merge()
3249 wm->enable = false; in ilk_wm_merge()
3250 else if (!ilk_validate_wm_level(level, max, wm)) in ilk_wm_merge()
3258 if (wm->fbc_val > max->fbc) { in ilk_wm_merge()
3259 if (wm->enable) in ilk_wm_merge()
3261 wm->fbc_val = 0; in ilk_wm_merge()
3274 struct intel_wm_level *wm = &merged->wm[level]; in ilk_wm_merge() local
3276 wm->enable = false; in ilk_wm_merge()
3284 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); in ilk_wm_lp_to_level()
3295 return dev_priv->wm.pri_latency[level]; in ilk_wm_lp_latency()
3316 r = &merged->wm[level]; in ilk_compute_wm_results()
3352 &intel_crtc->wm.active.ilk.wm[0]; in ilk_compute_wm_results()
3357 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime; in ilk_compute_wm_results()
3376 if (r1->wm[level].enable) in ilk_find_best_result()
3378 if (r2->wm[level].enable) in ilk_find_best_result()
3457 struct ilk_wm_values *previous = &dev_priv->wm.hw; in _ilk_disable_lp_wm()
3491 struct ilk_wm_values *previous = &dev_priv->wm.hw; in ilk_write_wm_values()
3560 dev_priv->wm.hw = *results; in ilk_write_wm_values()
3743 struct skl_plane_wm *wm = in intel_can_enable_sagv() local
3744 &cstate->wm.skl.optimal.planes[plane->id]; in intel_can_enable_sagv()
3747 if (!wm->wm[0].plane_en) in intel_can_enable_sagv()
3752 !wm->wm[level].plane_en; --level) in intel_can_enable_sagv()
3755 latency = dev_priv->wm.skl_latency[level]; in intel_can_enable_sagv()
3848 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb; in skl_ddb_get_pipe_allocation_limits()
4283 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb; in skl_allocate_pipe_ddb()
4598 uint32_t latency = dev_priv->wm.skl_latency[level]; in skl_compute_plane_wm()
4743 struct skl_plane_wm *wm, in skl_compute_wm_levels() argument
4763 struct skl_wm_level *result = plane_id ? &wm->uv_wm[level] : in skl_compute_wm_levels()
4764 &wm->wm[level]; in skl_compute_wm_levels()
4768 result_prev = plane_id ? &wm->uv_wm[level - 1] : in skl_compute_wm_levels()
4769 &wm->wm[level - 1]; in skl_compute_wm_levels()
4771 result_prev = plane_id ? &wm->uv_wm[0] : &wm->wm[0]; in skl_compute_wm_levels()
4786 wm->is_planar = true; in skl_compute_wm_levels()
4878 struct skl_plane_wm *wm; in skl_build_pipe_wm() local
4895 wm = &pipe_wm->planes[plane_id]; in skl_build_pipe_wm()
4904 intel_pstate, &wm_params, wm, 0); in skl_build_pipe_wm()
4908 skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0], in skl_build_pipe_wm()
4909 ddb_blocks, &wm->trans_wm); in skl_build_pipe_wm()
4914 wm->is_planar = true; in skl_build_pipe_wm()
4924 wm, 1); in skl_build_pipe_wm()
4961 const struct skl_plane_wm *wm, in skl_write_plane_wm() argument
4973 &wm->wm[level]); in skl_write_plane_wm()
4976 &wm->trans_wm); in skl_write_plane_wm()
4984 if (wm->is_planar) { in skl_write_plane_wm()
4998 const struct skl_plane_wm *wm, in skl_write_cursor_wm() argument
5009 &wm->wm[level]); in skl_write_cursor_wm()
5011 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm); in skl_write_cursor_wm()
5097 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; in skl_ddb_add_affected_planes()
5129 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb)); in skl_compute_ddb()
5165 const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb; in skl_print_wm_changes()
5208 if (dev_priv->wm.distrust_bios_wm) in skl_ddb_add_affected_pipes()
5231 if (dev_priv->wm.distrust_bios_wm) { in skl_ddb_add_affected_pipes()
5318 &to_intel_crtc_state(crtc->state)->wm.skl.optimal; in skl_compute_wm()
5320 pipe_wm = &intel_cstate->wm.skl.optimal; in skl_compute_wm()
5346 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal; in skl_atomic_update_crtc_wm()
5373 struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw; in skl_initial_wm()
5379 mutex_lock(&dev_priv->wm.wm_mutex); in skl_initial_wm()
5386 mutex_unlock(&dev_priv->wm.wm_mutex); in skl_initial_wm()
5396 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk; in ilk_compute_wm_config() local
5398 if (!wm->pipe_enabled) in ilk_compute_wm_config()
5401 config->sprites_enabled |= wm->sprites_enabled; in ilk_compute_wm_config()
5402 config->sprites_scaled |= wm->sprites_scaled; in ilk_compute_wm_config()
5446 mutex_lock(&dev_priv->wm.wm_mutex); in ilk_initial_watermarks()
5447 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate; in ilk_initial_watermarks()
5449 mutex_unlock(&dev_priv->wm.wm_mutex); in ilk_initial_watermarks()
5458 mutex_lock(&dev_priv->wm.wm_mutex); in ilk_optimize_watermarks()
5459 if (cstate->wm.need_postvbl_update) { in ilk_optimize_watermarks()
5460 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal; in ilk_optimize_watermarks()
5463 mutex_unlock(&dev_priv->wm.wm_mutex); in ilk_optimize_watermarks()
5488 struct skl_plane_wm *wm = &out->planes[plane_id]; in skl_pipe_wm_get_hw_state() local
5496 skl_wm_level_from_reg_val(val, &wm->wm[level]); in skl_pipe_wm_get_hw_state()
5504 skl_wm_level_from_reg_val(val, &wm->trans_wm); in skl_pipe_wm_get_hw_state()
5516 struct skl_ddb_values *hw = &dev_priv->wm.skl_hw; in skl_wm_get_hw_state()
5517 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; in skl_wm_get_hw_state()
5527 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal); in skl_wm_get_hw_state()
5535 dev_priv->wm.distrust_bios_wm = true; in skl_wm_get_hw_state()
5550 struct ilk_wm_values *hw = &dev_priv->wm.hw; in ilk_pipe_wm_get_hw_state()
5553 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal; in ilk_pipe_wm_get_hw_state()
5578 active->wm[0].enable = true; in ilk_pipe_wm_get_hw_state()
5579 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; in ilk_pipe_wm_get_hw_state()
5580 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; in ilk_pipe_wm_get_hw_state()
5581 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; in ilk_pipe_wm_get_hw_state()
5592 active->wm[level].enable = true; in ilk_pipe_wm_get_hw_state()
5595 intel_crtc->wm.active.ilk = *active; in ilk_pipe_wm_get_hw_state()
5604 struct g4x_wm_values *wm) in g4x_read_wm_values() argument
5609 wm->sr.plane = _FW_WM(tmp, SR); in g4x_read_wm_values()
5610 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); in g4x_read_wm_values()
5611 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB); in g4x_read_wm_values()
5612 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA); in g4x_read_wm_values()
5615 wm->fbc_en = tmp & DSPFW_FBC_SR_EN; in g4x_read_wm_values()
5616 wm->sr.fbc = _FW_WM(tmp, FBC_SR); in g4x_read_wm_values()
5617 wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR); in g4x_read_wm_values()
5618 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB); in g4x_read_wm_values()
5619 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); in g4x_read_wm_values()
5620 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA); in g4x_read_wm_values()
5623 wm->hpll_en = tmp & DSPFW_HPLL_SR_EN; in g4x_read_wm_values()
5624 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); in g4x_read_wm_values()
5625 wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR); in g4x_read_wm_values()
5626 wm->hpll.plane = _FW_WM(tmp, HPLL_SR); in g4x_read_wm_values()
5630 struct vlv_wm_values *wm) in vlv_read_wm_values() argument
5638 wm->ddl[pipe].plane[PLANE_PRIMARY] = in vlv_read_wm_values()
5640 wm->ddl[pipe].plane[PLANE_CURSOR] = in vlv_read_wm_values()
5642 wm->ddl[pipe].plane[PLANE_SPRITE0] = in vlv_read_wm_values()
5644 wm->ddl[pipe].plane[PLANE_SPRITE1] = in vlv_read_wm_values()
5649 wm->sr.plane = _FW_WM(tmp, SR); in vlv_read_wm_values()
5650 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); in vlv_read_wm_values()
5651 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB); in vlv_read_wm_values()
5652 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA); in vlv_read_wm_values()
5655 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB); in vlv_read_wm_values()
5656 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); in vlv_read_wm_values()
5657 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA); in vlv_read_wm_values()
5660 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); in vlv_read_wm_values()
5664 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); in vlv_read_wm_values()
5665 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); in vlv_read_wm_values()
5668 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF); in vlv_read_wm_values()
5669 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE); in vlv_read_wm_values()
5672 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC); in vlv_read_wm_values()
5673 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC); in vlv_read_wm_values()
5676 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; in vlv_read_wm_values()
5677 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8; in vlv_read_wm_values()
5678 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8; in vlv_read_wm_values()
5679 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8; in vlv_read_wm_values()
5680 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; in vlv_read_wm_values()
5681 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; in vlv_read_wm_values()
5682 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; in vlv_read_wm_values()
5683 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; in vlv_read_wm_values()
5684 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; in vlv_read_wm_values()
5685 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; in vlv_read_wm_values()
5688 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); in vlv_read_wm_values()
5689 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); in vlv_read_wm_values()
5692 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; in vlv_read_wm_values()
5693 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; in vlv_read_wm_values()
5694 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; in vlv_read_wm_values()
5695 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; in vlv_read_wm_values()
5696 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; in vlv_read_wm_values()
5697 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; in vlv_read_wm_values()
5698 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; in vlv_read_wm_values()
5708 struct g4x_wm_values *wm = &dev_priv->wm.g4x; in g4x_wm_get_hw_state() local
5711 g4x_read_wm_values(dev_priv, wm); in g4x_wm_get_hw_state()
5713 wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; in g4x_wm_get_hw_state()
5718 struct g4x_wm_state *active = &crtc->wm.active.g4x; in g4x_wm_get_hw_state()
5724 active->cxsr = wm->cxsr; in g4x_wm_get_hw_state()
5725 active->hpll_en = wm->hpll_en; in g4x_wm_get_hw_state()
5726 active->fbc_en = wm->fbc_en; in g4x_wm_get_hw_state()
5728 active->sr = wm->sr; in g4x_wm_get_hw_state()
5729 active->hpll = wm->hpll; in g4x_wm_get_hw_state()
5732 active->wm.plane[plane_id] = in g4x_wm_get_hw_state()
5733 wm->pipe[pipe].plane[plane_id]; in g4x_wm_get_hw_state()
5736 if (wm->cxsr && wm->hpll_en) in g4x_wm_get_hw_state()
5738 else if (wm->cxsr) in g4x_wm_get_hw_state()
5744 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
5746 raw->plane[plane_id] = active->wm.plane[plane_id]; in g4x_wm_get_hw_state()
5751 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
5760 raw = &crtc_state->wm.g4x.raw[level]; in g4x_wm_get_hw_state()
5772 crtc_state->wm.g4x.optimal = *active; in g4x_wm_get_hw_state()
5773 crtc_state->wm.g4x.intermediate = *active; in g4x_wm_get_hw_state()
5777 wm->pipe[pipe].plane[PLANE_PRIMARY], in g4x_wm_get_hw_state()
5778 wm->pipe[pipe].plane[PLANE_CURSOR], in g4x_wm_get_hw_state()
5779 wm->pipe[pipe].plane[PLANE_SPRITE0]); in g4x_wm_get_hw_state()
5783 wm->sr.plane, wm->sr.cursor, wm->sr.fbc); in g4x_wm_get_hw_state()
5785 wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc); in g4x_wm_get_hw_state()
5787 yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en)); in g4x_wm_get_hw_state()
5795 mutex_lock(&dev_priv->wm.wm_mutex); in g4x_wm_sanitize()
5804 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
5813 &crtc_state->wm.g4x.raw[level]; in g4x_wm_sanitize()
5816 wm_state->wm.plane[plane_id] = 0; in g4x_wm_sanitize()
5822 &crtc_state->wm.g4x.raw[level]; in g4x_wm_sanitize()
5836 crtc_state->wm.g4x.intermediate = in g4x_wm_sanitize()
5837 crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
5838 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; in g4x_wm_sanitize()
5843 mutex_unlock(&dev_priv->wm.wm_mutex); in g4x_wm_sanitize()
5849 struct vlv_wm_values *wm = &dev_priv->wm.vlv; in vlv_wm_get_hw_state() local
5853 vlv_read_wm_values(dev_priv, wm); in vlv_wm_get_hw_state()
5855 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; in vlv_wm_get_hw_state()
5856 wm->level = VLV_WM_LEVEL_PM2; in vlv_wm_get_hw_state()
5863 wm->level = VLV_WM_LEVEL_PM5; in vlv_wm_get_hw_state()
5882 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; in vlv_wm_get_hw_state()
5886 wm->level = VLV_WM_LEVEL_DDR_DVFS; in vlv_wm_get_hw_state()
5895 struct vlv_wm_state *active = &crtc->wm.active.vlv; in vlv_wm_get_hw_state()
5897 &crtc_state->wm.vlv.fifo_state; in vlv_wm_get_hw_state()
5904 active->num_levels = wm->level + 1; in vlv_wm_get_hw_state()
5905 active->cxsr = wm->cxsr; in vlv_wm_get_hw_state()
5909 &crtc_state->wm.vlv.raw[level]; in vlv_wm_get_hw_state()
5911 active->sr[level].plane = wm->sr.plane; in vlv_wm_get_hw_state()
5912 active->sr[level].cursor = wm->sr.cursor; in vlv_wm_get_hw_state()
5915 active->wm[level].plane[plane_id] = in vlv_wm_get_hw_state()
5916 wm->pipe[pipe].plane[plane_id]; in vlv_wm_get_hw_state()
5919 vlv_invert_wm_value(active->wm[level].plane[plane_id], in vlv_wm_get_hw_state()
5929 crtc_state->wm.vlv.optimal = *active; in vlv_wm_get_hw_state()
5930 crtc_state->wm.vlv.intermediate = *active; in vlv_wm_get_hw_state()
5934 wm->pipe[pipe].plane[PLANE_PRIMARY], in vlv_wm_get_hw_state()
5935 wm->pipe[pipe].plane[PLANE_CURSOR], in vlv_wm_get_hw_state()
5936 wm->pipe[pipe].plane[PLANE_SPRITE0], in vlv_wm_get_hw_state()
5937 wm->pipe[pipe].plane[PLANE_SPRITE1]); in vlv_wm_get_hw_state()
5941 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); in vlv_wm_get_hw_state()
5949 mutex_lock(&dev_priv->wm.wm_mutex); in vlv_wm_sanitize()
5958 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()
5960 &crtc_state->wm.vlv.fifo_state; in vlv_wm_sanitize()
5969 &crtc_state->wm.vlv.raw[level]; in vlv_wm_sanitize()
5973 wm_state->wm[level].plane[plane_id] = in vlv_wm_sanitize()
5983 crtc_state->wm.vlv.intermediate = in vlv_wm_sanitize()
5984 crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()
5985 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; in vlv_wm_sanitize()
5990 mutex_unlock(&dev_priv->wm.wm_mutex); in vlv_wm_sanitize()
6012 struct ilk_wm_values *hw = &dev_priv->wm.hw; in ilk_wm_get_hw_state()
9297 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] && in intel_init_pm()
9298 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || in intel_init_pm()
9299 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] && in intel_init_pm()
9300 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { in intel_init_pm()