446 		dev_priv->wm.vlv.cxsr = enable;  in intel_set_memory_cxsr()
477 	struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;  in vlv_get_fifo_size()
1648 		&crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];  in vlv_compute_fifo()
1649 	struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;  in vlv_compute_fifo()
1763 		struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];  in vlv_raw_plane_wm_set()
1787 		struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];  in vlv_raw_plane_wm_compute()
1805 			      crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],  in vlv_raw_plane_wm_compute()
1806 			      crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],  in vlv_raw_plane_wm_compute()
1807 			      crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);  in vlv_raw_plane_wm_compute()
1816 		&crtc_state->wm.vlv.raw[level];  in vlv_raw_plane_wm_is_valid()
1818 		&crtc_state->wm.vlv.fifo_state;  in vlv_raw_plane_wm_is_valid()
1837 	struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;  in vlv_compute_pipe_wm()
1839 		&crtc_state->wm.vlv.fifo_state;  in vlv_compute_pipe_wm()
1878 			&old_crtc_state->wm.vlv.fifo_state;  in vlv_compute_pipe_wm()
1900 		const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];  in vlv_compute_pipe_wm()
1944 		&crtc_state->wm.vlv.fifo_state;  in vlv_atomic_update_fifo()
2038 	struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;  in vlv_compute_intermediate_wm()
2039 	const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;  in vlv_compute_intermediate_wm()
2044 	const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;  in vlv_compute_intermediate_wm()
2096 		const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;  in vlv_merge_wm()
2115 		const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;  in vlv_merge_wm()
2131 	struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;  in vlv_program_watermarks()
2169 	crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;  in vlv_initial_watermarks()
2184 	intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;  in vlv_optimize_watermarks()
5849 	struct vlv_wm_values *wm = &dev_priv->wm.vlv;  in vlv_wm_get_hw_state()
5895 		struct vlv_wm_state *active = &crtc->wm.active.vlv;  in vlv_wm_get_hw_state()
5897 			&crtc_state->wm.vlv.fifo_state;  in vlv_wm_get_hw_state()
5909 				&crtc_state->wm.vlv.raw[level];  in vlv_wm_get_hw_state()
5929 		crtc_state->wm.vlv.optimal = *active;  in vlv_wm_get_hw_state()
5930 		crtc_state->wm.vlv.intermediate = *active;  in vlv_wm_get_hw_state()
5958 		struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;  in vlv_wm_sanitize()
5960 			&crtc_state->wm.vlv.fifo_state;  in vlv_wm_sanitize()
5969 				&crtc_state->wm.vlv.raw[level];  in vlv_wm_sanitize()
5983 		crtc_state->wm.vlv.intermediate =  in vlv_wm_sanitize()
5984 			crtc_state->wm.vlv.optimal;  in vlv_wm_sanitize()
5985 		crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;  in vlv_wm_sanitize()