Lines Matching refs:plane_id
1049 static int g4x_plane_fifo_size(enum plane_id plane_id, int level) in g4x_plane_fifo_size() argument
1065 switch (plane_id) { in g4x_plane_fifo_size()
1073 MISSING_CASE(plane_id); in g4x_plane_fifo_size()
1156 int level, enum plane_id plane_id, u16 value) in g4x_raw_plane_wm_set() argument
1164 dirty |= raw->plane[plane_id] != value; in g4x_raw_plane_wm_set()
1165 raw->plane[plane_id] = value; in g4x_raw_plane_wm_set()
1199 enum plane_id plane_id = plane->id; in g4x_raw_plane_wm_compute() local
1204 dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0); in g4x_raw_plane_wm_compute()
1205 if (plane_id == PLANE_PRIMARY) in g4x_raw_plane_wm_compute()
1215 max_wm = g4x_plane_fifo_size(plane_id, level); in g4x_raw_plane_wm_compute()
1220 dirty |= raw->plane[plane_id] != wm; in g4x_raw_plane_wm_compute()
1221 raw->plane[plane_id] = wm; in g4x_raw_plane_wm_compute()
1223 if (plane_id != PLANE_PRIMARY || in g4x_raw_plane_wm_compute()
1228 raw->plane[plane_id]); in g4x_raw_plane_wm_compute()
1243 dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX); in g4x_raw_plane_wm_compute()
1245 if (plane_id == PLANE_PRIMARY) in g4x_raw_plane_wm_compute()
1252 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id], in g4x_raw_plane_wm_compute()
1253 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id], in g4x_raw_plane_wm_compute()
1254 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]); in g4x_raw_plane_wm_compute()
1256 if (plane_id == PLANE_PRIMARY) in g4x_raw_plane_wm_compute()
1266 enum plane_id plane_id, int level) in g4x_raw_plane_wm_is_valid() argument
1270 return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level); in g4x_raw_plane_wm_is_valid()
1291 enum plane_id plane_id; in g4x_invalidate_wms() local
1293 for_each_plane_id_on_crtc(crtc, plane_id) in g4x_invalidate_wms()
1294 wm_state->wm.plane[plane_id] = USHRT_MAX; in g4x_invalidate_wms()
1324 enum plane_id plane_id; in g4x_compute_pipe_wm() local
1347 for_each_plane_id_on_crtc(crtc, plane_id) in g4x_compute_pipe_wm()
1348 wm_state->wm.plane[plane_id] = raw->plane[plane_id]; in g4x_compute_pipe_wm()
1412 enum plane_id plane_id; in g4x_compute_intermediate_wm() local
1428 for_each_plane_id_on_crtc(crtc, plane_id) { in g4x_compute_intermediate_wm()
1429 intermediate->wm.plane[plane_id] = in g4x_compute_intermediate_wm()
1430 max(optimal->wm.plane[plane_id], in g4x_compute_intermediate_wm()
1431 active->wm.plane[plane_id]); in g4x_compute_intermediate_wm()
1433 WARN_ON(intermediate->wm.plane[plane_id] > in g4x_compute_intermediate_wm()
1434 g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL)); in g4x_compute_intermediate_wm()
1656 enum plane_id plane_id; in vlv_compute_fifo() local
1680 for_each_plane_id_on_crtc(crtc, plane_id) { in vlv_compute_fifo()
1683 if ((active_planes & BIT(plane_id)) == 0) { in vlv_compute_fifo()
1684 fifo_state->plane[plane_id] = 0; in vlv_compute_fifo()
1688 rate = raw->plane[plane_id]; in vlv_compute_fifo()
1689 fifo_state->plane[plane_id] = fifo_size * rate / total_rate; in vlv_compute_fifo()
1690 fifo_left -= fifo_state->plane[plane_id]; in vlv_compute_fifo()
1701 for_each_plane_id_on_crtc(crtc, plane_id) { in vlv_compute_fifo()
1707 if ((active_planes & BIT(plane_id)) == 0) in vlv_compute_fifo()
1711 fifo_state->plane[plane_id] += plane_extra; in vlv_compute_fifo()
1733 enum plane_id plane_id; in vlv_invalidate_wms() local
1735 for_each_plane_id_on_crtc(crtc, plane_id) in vlv_invalidate_wms()
1736 wm_state->wm[level].plane[plane_id] = USHRT_MAX; in vlv_invalidate_wms()
1756 int level, enum plane_id plane_id, u16 value) in vlv_raw_plane_wm_set() argument
1765 dirty |= raw->plane[plane_id] != value; in vlv_raw_plane_wm_set()
1766 raw->plane[plane_id] = value; in vlv_raw_plane_wm_set()
1776 enum plane_id plane_id = plane->id; in vlv_raw_plane_wm_compute() local
1782 dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0); in vlv_raw_plane_wm_compute()
1789 int max_wm = plane_id == PLANE_CURSOR ? 63 : 511; in vlv_raw_plane_wm_compute()
1794 dirty |= raw->plane[plane_id] != wm; in vlv_raw_plane_wm_compute()
1795 raw->plane[plane_id] = wm; in vlv_raw_plane_wm_compute()
1799 dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX); in vlv_raw_plane_wm_compute()
1805 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], in vlv_raw_plane_wm_compute()
1806 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], in vlv_raw_plane_wm_compute()
1807 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); in vlv_raw_plane_wm_compute()
1813 enum plane_id plane_id, int level) in vlv_raw_plane_wm_is_valid() argument
1820 return raw->plane[plane_id] <= fifo_state->plane[plane_id]; in vlv_raw_plane_wm_is_valid()
1846 enum plane_id plane_id; in vlv_compute_pipe_wm() local
1906 for_each_plane_id_on_crtc(crtc, plane_id) { in vlv_compute_pipe_wm()
1907 wm_state->wm[level].plane[plane_id] = in vlv_compute_pipe_wm()
1908 vlv_invert_wm_value(raw->plane[plane_id], in vlv_compute_pipe_wm()
1909 fifo_state->plane[plane_id]); in vlv_compute_pipe_wm()
2059 enum plane_id plane_id; in vlv_compute_intermediate_wm() local
2061 for_each_plane_id_on_crtc(crtc, plane_id) { in vlv_compute_intermediate_wm()
2062 intermediate->wm[level].plane[plane_id] = in vlv_compute_intermediate_wm()
2063 min(optimal->wm[level].plane[plane_id], in vlv_compute_intermediate_wm()
2064 active->wm[level].plane[plane_id]); in vlv_compute_intermediate_wm()
3886 const enum plane_id plane_id, in skl_ddb_get_hw_plane_state() argument
3893 if (plane_id == PLANE_CURSOR) { in skl_ddb_get_hw_plane_state()
3896 &ddb->plane[pipe][plane_id], val); in skl_ddb_get_hw_plane_state()
3900 val = I915_READ(PLANE_CTL(pipe, plane_id)); in skl_ddb_get_hw_plane_state()
3911 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id)); in skl_ddb_get_hw_plane_state()
3912 val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id)); in skl_ddb_get_hw_plane_state()
3916 &ddb->plane[pipe][plane_id], val2); in skl_ddb_get_hw_plane_state()
3918 &ddb->uv_plane[pipe][plane_id], val); in skl_ddb_get_hw_plane_state()
3921 &ddb->plane[pipe][plane_id], val); in skl_ddb_get_hw_plane_state()
3936 enum plane_id plane_id; in skl_ddb_get_hw_state() local
3943 for_each_plane_id_on_crtc(crtc, plane_id) in skl_ddb_get_hw_state()
3945 plane_id, ddb); in skl_ddb_get_hw_state()
4167 enum plane_id plane_id = to_intel_plane(plane)->id; in skl_get_total_relative_data_rate() local
4173 plane_data_rate[plane_id] = rate; in skl_get_total_relative_data_rate()
4180 uv_plane_data_rate[plane_id] = rate; in skl_get_total_relative_data_rate()
4259 enum plane_id plane_id = to_intel_plane(plane)->id; in skl_ddb_calc_min() local
4261 if (plane_id == PLANE_CURSOR) in skl_ddb_calc_min()
4267 minimum[plane_id] = skl_ddb_min_alloc(pstate, 0); in skl_ddb_calc_min()
4268 uv_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1); in skl_ddb_calc_min()
4288 enum plane_id plane_id; in skl_allocate_pipe_ddb() local
4323 for_each_plane_id_on_crtc(intel_crtc, plane_id) { in skl_allocate_pipe_ddb()
4324 total_min_blocks += minimum[plane_id]; in skl_allocate_pipe_ddb()
4325 total_min_blocks += uv_minimum[plane_id]; in skl_allocate_pipe_ddb()
4349 for_each_plane_id_on_crtc(intel_crtc, plane_id) { in skl_allocate_pipe_ddb()
4353 if (plane_id == PLANE_CURSOR) in skl_allocate_pipe_ddb()
4356 data_rate = plane_data_rate[plane_id]; in skl_allocate_pipe_ddb()
4363 plane_blocks = minimum[plane_id]; in skl_allocate_pipe_ddb()
4369 ddb->plane[pipe][plane_id].start = start; in skl_allocate_pipe_ddb()
4370 ddb->plane[pipe][plane_id].end = start + plane_blocks; in skl_allocate_pipe_ddb()
4376 uv_data_rate = uv_plane_data_rate[plane_id]; in skl_allocate_pipe_ddb()
4378 uv_plane_blocks = uv_minimum[plane_id]; in skl_allocate_pipe_ddb()
4383 ddb->uv_plane[pipe][plane_id].start = start; in skl_allocate_pipe_ddb()
4384 ddb->uv_plane[pipe][plane_id].end = in skl_allocate_pipe_ddb()
4484 struct skl_wm_params *wp, int plane_id) in skl_compute_plane_wm_params() argument
4498 if (plane_id == 1 && fb->format->format != DRM_FORMAT_NV12) { in skl_compute_plane_wm_params()
4523 if (plane_id == 1 && wp->is_planar) in skl_compute_plane_wm_params()
4526 wp->cpp = fb->format->cpp[plane_id]; in skl_compute_plane_wm_params()
4744 int plane_id) in skl_compute_wm_levels() argument
4752 enum plane_id intel_plane_id = intel_plane->id; in skl_compute_wm_levels()
4758 ddb_blocks = plane_id ? in skl_compute_wm_levels()
4763 struct skl_wm_level *result = plane_id ? &wm->uv_wm[level] : in skl_compute_wm_levels()
4768 result_prev = plane_id ? &wm->uv_wm[level - 1] : in skl_compute_wm_levels()
4771 result_prev = plane_id ? &wm->uv_wm[0] : &wm->wm[0]; in skl_compute_wm_levels()
4890 enum plane_id plane_id = to_intel_plane(plane)->id; in skl_build_pipe_wm() local
4895 wm = &pipe_wm->planes[plane_id]; in skl_build_pipe_wm()
4896 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]); in skl_build_pipe_wm()
4963 enum plane_id plane_id) in skl_write_plane_wm() argument
4972 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level), in skl_write_plane_wm()
4975 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id), in skl_write_plane_wm()
4978 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id), in skl_write_plane_wm()
4979 &ddb->plane[pipe][plane_id]); in skl_write_plane_wm()
4982 PLANE_BUF_CFG(pipe, plane_id), in skl_write_plane_wm()
4983 &ddb->plane[pipe][plane_id]); in skl_write_plane_wm()
4985 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id), in skl_write_plane_wm()
4986 &ddb->uv_plane[pipe][plane_id]); in skl_write_plane_wm()
4988 PLANE_NV12_BUF_CFG(pipe, plane_id), in skl_write_plane_wm()
4989 &ddb->plane[pipe][plane_id]); in skl_write_plane_wm()
4991 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id), in skl_write_plane_wm()
4992 &ddb->plane[pipe][plane_id]); in skl_write_plane_wm()
4993 I915_WRITE(PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0); in skl_write_plane_wm()
5103 enum plane_id plane_id = to_intel_plane(plane)->id; in skl_ddb_add_affected_planes() local
5105 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id], in skl_ddb_add_affected_planes()
5106 &new_ddb->plane[pipe][plane_id]) && in skl_ddb_add_affected_planes()
5107 skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id], in skl_ddb_add_affected_planes()
5108 &new_ddb->uv_plane[pipe][plane_id])) in skl_ddb_add_affected_planes()
5174 enum plane_id plane_id = intel_plane->id; in skl_print_wm_changes() local
5177 old = &old_ddb->plane[pipe][plane_id]; in skl_print_wm_changes()
5178 new = &new_ddb->plane[pipe][plane_id]; in skl_print_wm_changes()
5349 enum plane_id plane_id; in skl_atomic_update_crtc_wm() local
5356 for_each_plane_id_on_crtc(crtc, plane_id) { in skl_atomic_update_crtc_wm()
5357 if (plane_id != PLANE_CURSOR) in skl_atomic_update_crtc_wm()
5358 skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id], in skl_atomic_update_crtc_wm()
5359 ddb, plane_id); in skl_atomic_update_crtc_wm()
5361 skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id], in skl_atomic_update_crtc_wm()
5482 enum plane_id plane_id; in skl_pipe_wm_get_hw_state() local
5487 for_each_plane_id_on_crtc(intel_crtc, plane_id) { in skl_pipe_wm_get_hw_state()
5488 struct skl_plane_wm *wm = &out->planes[plane_id]; in skl_pipe_wm_get_hw_state()
5491 if (plane_id != PLANE_CURSOR) in skl_pipe_wm_get_hw_state()
5492 val = I915_READ(PLANE_WM(pipe, plane_id, level)); in skl_pipe_wm_get_hw_state()
5499 if (plane_id != PLANE_CURSOR) in skl_pipe_wm_get_hw_state()
5500 val = I915_READ(PLANE_WM_TRANS(pipe, plane_id)); in skl_pipe_wm_get_hw_state()
5721 enum plane_id plane_id; in g4x_wm_get_hw_state() local
5731 for_each_plane_id_on_crtc(crtc, plane_id) { in g4x_wm_get_hw_state()
5732 active->wm.plane[plane_id] = in g4x_wm_get_hw_state()
5733 wm->pipe[pipe].plane[plane_id]; in g4x_wm_get_hw_state()
5745 for_each_plane_id_on_crtc(crtc, plane_id) in g4x_wm_get_hw_state()
5746 raw->plane[plane_id] = active->wm.plane[plane_id]; in g4x_wm_get_hw_state()
5767 for_each_plane_id_on_crtc(crtc, plane_id) in g4x_wm_get_hw_state()
5769 plane_id, USHRT_MAX); in g4x_wm_get_hw_state()
5805 enum plane_id plane_id = plane->id; in g4x_wm_sanitize() local
5815 raw->plane[plane_id] = 0; in g4x_wm_sanitize()
5816 wm_state->wm.plane[plane_id] = 0; in g4x_wm_sanitize()
5819 if (plane_id == PLANE_PRIMARY) { in g4x_wm_sanitize()
5899 enum plane_id plane_id; in vlv_wm_get_hw_state() local
5914 for_each_plane_id_on_crtc(crtc, plane_id) { in vlv_wm_get_hw_state()
5915 active->wm[level].plane[plane_id] = in vlv_wm_get_hw_state()
5916 wm->pipe[pipe].plane[plane_id]; in vlv_wm_get_hw_state()
5918 raw->plane[plane_id] = in vlv_wm_get_hw_state()
5919 vlv_invert_wm_value(active->wm[level].plane[plane_id], in vlv_wm_get_hw_state()
5920 fifo_state->plane[plane_id]); in vlv_wm_get_hw_state()
5924 for_each_plane_id_on_crtc(crtc, plane_id) in vlv_wm_get_hw_state()
5926 plane_id, USHRT_MAX); in vlv_wm_get_hw_state()
5961 enum plane_id plane_id = plane->id; in vlv_wm_sanitize() local
5971 raw->plane[plane_id] = 0; in vlv_wm_sanitize()
5973 wm_state->wm[level].plane[plane_id] = in vlv_wm_sanitize()
5974 vlv_invert_wm_value(raw->plane[plane_id], in vlv_wm_sanitize()
5975 fifo_state->plane[plane_id]); in vlv_wm_sanitize()