207 	dev_priv->ips.r_t = dev_priv->mem_freq;  in i915_ironlake_get_mem_freq()
239 		dev_priv->ips.c_m = 0;  in i915_ironlake_get_mem_freq()
241 		dev_priv->ips.c_m = 1;  in i915_ironlake_get_mem_freq()
243 		dev_priv->ips.c_m = 2;  in i915_ironlake_get_mem_freq()
6176 	dev_priv->ips.fmax = fmax; /* IPS callback will increase this */  in ironlake_enable_drps()
6177 	dev_priv->ips.fstart = fstart;  in ironlake_enable_drps()
6179 	dev_priv->ips.max_delay = fstart;  in ironlake_enable_drps()
6180 	dev_priv->ips.min_delay = fmin;  in ironlake_enable_drps()
6181 	dev_priv->ips.cur_delay = fstart;  in ironlake_enable_drps()
6204 	dev_priv->ips.last_count1 = I915_READ(DMIEC) +  in ironlake_enable_drps()
6206 	dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);  in ironlake_enable_drps()
6207 	dev_priv->ips.last_count2 = I915_READ(GFXEC);  in ironlake_enable_drps()
6208 	dev_priv->ips.last_time2 = ktime_get_raw_ns();  in ironlake_enable_drps()
6229 	ironlake_set_drps(dev_priv, dev_priv->ips.fstart);  in ironlake_disable_drps()
7717 	diff1 = now - dev_priv->ips.last_time1;  in __i915_chipset_val()
7725 		return dev_priv->ips.chipset_power;  in __i915_chipset_val()
7734 	if (total_count < dev_priv->ips.last_count1) {  in __i915_chipset_val()
7735 		diff = ~0UL - dev_priv->ips.last_count1;  in __i915_chipset_val()
7738 		diff = total_count - dev_priv->ips.last_count1;  in __i915_chipset_val()
7742 		if (cparams[i].i == dev_priv->ips.c_m &&  in __i915_chipset_val()
7743 		    cparams[i].t == dev_priv->ips.r_t) {  in __i915_chipset_val()
7754 	dev_priv->ips.last_count1 = total_count;  in __i915_chipset_val()
7755 	dev_priv->ips.last_time1 = now;  in __i915_chipset_val()
7757 	dev_priv->ips.chipset_power = ret;  in __i915_chipset_val()
7823 	diffms = now - dev_priv->ips.last_time2;  in __i915_update_gfx_val()
7832 	if (count < dev_priv->ips.last_count2) {  in __i915_update_gfx_val()
7833 		diff = ~0UL - dev_priv->ips.last_count2;  in __i915_update_gfx_val()
7836 		diff = count - dev_priv->ips.last_count2;  in __i915_update_gfx_val()
7839 	dev_priv->ips.last_count2 = count;  in __i915_update_gfx_val()
7840 	dev_priv->ips.last_time2 = now;  in __i915_update_gfx_val()
7845 	dev_priv->ips.gfx_power = diff;  in __i915_update_gfx_val()
7887 	corr2 = (corr * dev_priv->ips.corr);  in __i915_gfx_val()
7894 	return dev_priv->ips.gfx_power + state2;  in __i915_gfx_val()
7958 	if (dev_priv->ips.max_delay > dev_priv->ips.fmax)  in i915_gpu_raise()
7959 		dev_priv->ips.max_delay--;  in i915_gpu_raise()
7986 	if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)  in i915_gpu_lower()
7987 		dev_priv->ips.max_delay++;  in i915_gpu_lower()
8032 	dev_priv->ips.max_delay = dev_priv->ips.fstart;  in i915_gpu_turbo_disable()
8034 	if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))  in i915_gpu_turbo_disable()
8149 	dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);  in intel_init_emon()