1407 	struct intel_atomic_state *intel_state =  in g4x_compute_intermediate_wm()  local
1410 		intel_atomic_get_old_crtc_state(intel_state, crtc);  in g4x_compute_intermediate_wm()
2040 	struct intel_atomic_state *intel_state =  in vlv_compute_intermediate_wm()  local
2043 		intel_atomic_get_old_crtc_state(intel_state, crtc);  in vlv_compute_intermediate_wm()
2774 	const struct intel_atomic_state *intel_state =  in hsw_compute_linetime_wm()  local
2784 	if (WARN_ON(intel_state->cdclk.logical.cdclk == 0))  in hsw_compute_linetime_wm()
2793 					 intel_state->cdclk.logical.cdclk);  in hsw_compute_linetime_wm()
3139 	struct intel_atomic_state *intel_state =  in ilk_compute_intermediate_wm()  local
3142 		intel_atomic_get_old_crtc_state(intel_state, intel_crtc);  in ilk_compute_intermediate_wm()
3705 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);  in intel_can_enable_sagv()  local
3729 	if (hweight32(intel_state->active_crtcs) == 0)  in intel_can_enable_sagv()
3731 	else if (hweight32(intel_state->active_crtcs) > 1)  in intel_can_enable_sagv()
3735 	pipe = ffs(intel_state->active_crtcs) - 1;  in intel_can_enable_sagv()
3757 		if (skl_needs_memory_bw_wa(intel_state) &&  in intel_can_enable_sagv()
3814 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);  in skl_ddb_get_pipe_allocation_limits()  local
3827 	if (intel_state->active_pipe_changes)  in skl_ddb_get_pipe_allocation_limits()
3828 		*num_active = hweight32(intel_state->active_crtcs);  in skl_ddb_get_pipe_allocation_limits()
3843 	if (!intel_state->active_pipe_changes) {  in skl_ddb_get_pipe_allocation_limits()
3852 	nth_active_pipe = hweight32(intel_state->active_crtcs &  in skl_ddb_get_pipe_allocation_limits()
3854 	pipe_size = ddb_size / hweight32(intel_state->active_crtcs);  in skl_ddb_get_pipe_allocation_limits()
5095 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);  in skl_ddb_add_affected_planes()  local
5096 	struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;  in skl_ddb_add_affected_planes()
5123 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);  in skl_compute_ddb()  local
5124 	struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;  in skl_compute_ddb()
5131 	for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {  in skl_compute_ddb()
5160 	const struct intel_atomic_state *intel_state =  in skl_print_wm_changes()  local
5166 	const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;  in skl_print_wm_changes()
5200 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);  in skl_ddb_add_affected_pipes()  local
5237 		intel_state->active_pipe_changes = ~0;  in skl_ddb_add_affected_pipes()
5245 		if (!intel_state->modeset)  in skl_ddb_add_affected_pipes()
5246 			intel_state->active_crtcs = dev_priv->active_crtcs;  in skl_ddb_add_affected_pipes()
5262 	if (intel_state->active_pipe_changes) {  in skl_ddb_add_affected_pipes()
5264 		intel_state->wm_results.dirty_pipes = ~0;  in skl_ddb_add_affected_pipes()
5287 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);  in skl_compute_wm()  local
5288 	struct skl_ddb_values *results = &intel_state->wm_results;  in skl_compute_wm()