6245 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in intel_rps_limits()
6269 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in rps_set_power()
6345 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in gen6_set_rps_thresholds()
6387 	struct intel_rps *rps = &i915->gt_pm.rps;  in intel_rps_mark_interactive()
6405 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in gen6_rps_pm_mask()
6424 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in gen6_set_rps()
6467 	if (val != dev_priv->gt_pm.rps.cur_freq) {  in valleyview_set_rps()
6475 	dev_priv->gt_pm.rps.cur_freq = val;  in valleyview_set_rps()
6490 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in vlv_set_rps_idle()
6519 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in gen6_rps_busy()
6549 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in gen6_rps_idle()
6574 	struct intel_rps *rps = &rq->i915->gt_pm.rps;  in gen6_rps_boost()
6606 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in intel_set_rps()
6762 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in gen6_init_rps_frequencies()
6811 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in reset_rps()
6830 			GEN9_FREQUENCY(dev_priv->gt_pm.rps.rp1_freq));  in gen9_enable_rps()
6973 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in gen8_enable_rps()
7100 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in gen6_update_ring_freq()
7391 	dev_priv->gt_pm.rps.gpll_ref_freq =  in vlv_init_gpll_ref_freq()
7397 			 dev_priv->gt_pm.rps.gpll_ref_freq);  in vlv_init_gpll_ref_freq()
7402 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in valleyview_init_gt_powersave()
7448 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in cherryview_init_gt_powersave()
7867 	pxvid = I915_READ(PXVFREQ(dev_priv->gt_pm.rps.cur_freq));  in __i915_gfx_val()
8154 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in intel_init_gt_powersave()
8235 	dev_priv->gt_pm.rps.enabled = true; /* force RPS disabling */  in intel_sanitize_gt_powersave()
8236 	dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */  in intel_sanitize_gt_powersave()
8249 	if (!i915->gt_pm.llc_pstate.enabled)  in intel_disable_llc_pstate()
8254 	i915->gt_pm.llc_pstate.enabled = false;  in intel_disable_llc_pstate()
8261 	if (!dev_priv->gt_pm.rc6.enabled)  in intel_disable_rc6()
8273 	dev_priv->gt_pm.rc6.enabled = false;  in intel_disable_rc6()
8280 	if (!dev_priv->gt_pm.rps.enabled)  in intel_disable_rps()
8294 	dev_priv->gt_pm.rps.enabled = false;  in intel_disable_rps()
8313 	if (i915->gt_pm.llc_pstate.enabled)  in intel_enable_llc_pstate()
8318 	i915->gt_pm.llc_pstate.enabled = true;  in intel_enable_llc_pstate()
8325 	if (dev_priv->gt_pm.rc6.enabled)  in intel_enable_rc6()
8339 	dev_priv->gt_pm.rc6.enabled = true;  in intel_enable_rc6()
8344 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in intel_enable_rps()
9575 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in byt_gpu_freq()
9586 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in byt_freq_opcode()
9593 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in chv_gpu_freq()
9604 	struct intel_rps *rps = &dev_priv->gt_pm.rps;  in chv_freq_opcode()
9639 	mutex_init(&dev_priv->gt_pm.rps.power.mutex);  in intel_pm_setup()
9641 	atomic_set(&dev_priv->gt_pm.rps.num_waiters, 0);  in intel_pm_setup()
9714 	if (WARN_ON_ONCE(i >= ARRAY_SIZE(dev_priv->gt_pm.rc6.cur_residency)))  in intel_rc6_residency_ns()
9748 	prev_hw = dev_priv->gt_pm.rc6.prev_hw_residency[i];  in intel_rc6_residency_ns()
9749 	dev_priv->gt_pm.rc6.prev_hw_residency[i] = time_hw;  in intel_rc6_residency_ns()
9758 	time_hw += dev_priv->gt_pm.rc6.cur_residency[i];  in intel_rc6_residency_ns()
9759 	dev_priv->gt_pm.rc6.cur_residency[i] = time_hw;  in intel_rc6_residency_ns()