3778 				       struct skl_ddb_allocation *ddb)  in intel_get_ddb_size()  argument
3796 		ddb->enabled_slices = 2;  in intel_get_ddb_size()
3798 		ddb->enabled_slices = 1;  in intel_get_ddb_size()
3809 				   struct skl_ddb_allocation *ddb,  in skl_ddb_get_pipe_allocation_limits()  argument
3833 				      *num_active, ddb);  in skl_ddb_get_pipe_allocation_limits()
3848 		*alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;  in skl_ddb_get_pipe_allocation_limits()
3887 			   struct skl_ddb_allocation *ddb /* out */)  in skl_ddb_get_hw_plane_state()  argument
3896 					   &ddb->plane[pipe][plane_id], val);  in skl_ddb_get_hw_plane_state()
3916 					   &ddb->plane[pipe][plane_id], val2);  in skl_ddb_get_hw_plane_state()
3918 					   &ddb->uv_plane[pipe][plane_id], val);  in skl_ddb_get_hw_plane_state()
3921 					   &ddb->plane[pipe][plane_id], val);  in skl_ddb_get_hw_plane_state()
3926 			  struct skl_ddb_allocation *ddb /* out */)  in skl_ddb_get_hw_state()  argument
3930 	memset(ddb, 0, sizeof(*ddb));  in skl_ddb_get_hw_state()
3932 	ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);  in skl_ddb_get_hw_state()
3945 						   plane_id, ddb);  in skl_ddb_get_hw_state()
4276 		      struct skl_ddb_allocation *ddb /* out */)  in skl_allocate_pipe_ddb()  argument
4283 	struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;  in skl_allocate_pipe_ddb()
4295 	memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));  in skl_allocate_pipe_ddb()
4296 	memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));  in skl_allocate_pipe_ddb()
4309 	skl_ddb_get_pipe_allocation_limits(dev, cstate, total_data_rate, ddb,  in skl_allocate_pipe_ddb()
4336 	ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];  in skl_allocate_pipe_ddb()
4337 	ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;  in skl_allocate_pipe_ddb()
4369 			ddb->plane[pipe][plane_id].start = start;  in skl_allocate_pipe_ddb()
4370 			ddb->plane[pipe][plane_id].end = start + plane_blocks;  in skl_allocate_pipe_ddb()
4383 			ddb->uv_plane[pipe][plane_id].start = start;  in skl_allocate_pipe_ddb()
4384 			ddb->uv_plane[pipe][plane_id].end =  in skl_allocate_pipe_ddb()
4739 		      struct skl_ddb_allocation *ddb,  in skl_compute_wm_levels()  argument
4759 		     skl_ddb_entry_size(&ddb->uv_plane[pipe][intel_plane_id]) :  in skl_compute_wm_levels()
4760 		     skl_ddb_entry_size(&ddb->plane[pipe][intel_plane_id]);  in skl_compute_wm_levels()
4870 			     struct skl_ddb_allocation *ddb,  in skl_build_pipe_wm()  argument
4896 		ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);  in skl_build_pipe_wm()
4903 		ret = skl_compute_wm_levels(dev_priv, ddb, cstate,  in skl_build_pipe_wm()
4922 			ret = skl_compute_wm_levels(dev_priv, ddb, cstate,  in skl_build_pipe_wm()
4962 			       const struct skl_ddb_allocation *ddb,  in skl_write_plane_wm()  argument
4979 			    &ddb->plane[pipe][plane_id]);  in skl_write_plane_wm()
4983 					   &ddb->plane[pipe][plane_id]);  in skl_write_plane_wm()
4986 				    &ddb->uv_plane[pipe][plane_id]);  in skl_write_plane_wm()
4989 				    &ddb->plane[pipe][plane_id]);  in skl_write_plane_wm()
4992 				    &ddb->plane[pipe][plane_id]);  in skl_write_plane_wm()
4999 				const struct skl_ddb_allocation *ddb)  in skl_write_cursor_wm()  argument
5014 			    &ddb->plane[pipe][PLANE_CURSOR]);  in skl_write_cursor_wm()
5039 				 const struct skl_ddb_entry *ddb,  in skl_ddb_allocation_overlaps()  argument
5046 		    skl_ddb_entries_overlap(ddb, entries[pipe]))  in skl_ddb_allocation_overlaps()
5056 			      struct skl_ddb_allocation *ddb, /* out */  in skl_update_pipe_wm()  argument
5062 	ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);  in skl_update_pipe_wm()
5096 	struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;  in skl_ddb_add_affected_planes()
5097 	struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;  in skl_ddb_add_affected_planes()
5124 	struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;  in skl_compute_ddb()  local
5129 	memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));  in skl_compute_ddb()
5132 		ret = skl_allocate_pipe_ddb(cstate, ddb);  in skl_compute_ddb()
5149 	memcpy(dst->ddb.uv_plane[pipe], src->ddb.uv_plane[pipe],  in skl_copy_ddb_for_pipe()
5150 	       sizeof(dst->ddb.uv_plane[pipe]));  in skl_copy_ddb_for_pipe()
5151 	memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],  in skl_copy_ddb_for_pipe()
5152 	       sizeof(dst->ddb.plane[pipe]));  in skl_copy_ddb_for_pipe()
5165 	const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;  in skl_print_wm_changes()
5166 	const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;  in skl_print_wm_changes()
5322 					 &results->ddb, &changed);  in skl_compute_wm()
5347 	const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;  in skl_atomic_update_crtc_wm()  local
5359 					   ddb, plane_id);  in skl_atomic_update_crtc_wm()
5362 					    ddb);  in skl_atomic_update_crtc_wm()
5517 	struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;  in skl_wm_get_hw_state()  local
5522 	skl_ddb_get_hw_state(dev_priv, ddb);  in skl_wm_get_hw_state()
5541 		memset(ddb->plane, 0, sizeof(ddb->plane));  in skl_wm_get_hw_state()
5542 		memset(ddb->uv_plane, 0, sizeof(ddb->uv_plane));  in skl_wm_get_hw_state()