1190 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
2487 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,  in ilk_compute_pri_wm()  argument
2495 	if (!intel_wm_plane_visible(cstate, pstate))  in ilk_compute_pri_wm()
2500 	method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);  in ilk_compute_pri_wm()
2505 	method2 = ilk_wm_method2(cstate->pixel_rate,  in ilk_compute_pri_wm()
2506 				 cstate->base.adjusted_mode.crtc_htotal,  in ilk_compute_pri_wm()
2517 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,  in ilk_compute_spr_wm()  argument
2524 	if (!intel_wm_plane_visible(cstate, pstate))  in ilk_compute_spr_wm()
2529 	method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value);  in ilk_compute_spr_wm()
2530 	method2 = ilk_wm_method2(cstate->pixel_rate,  in ilk_compute_spr_wm()
2531 				 cstate->base.adjusted_mode.crtc_htotal,  in ilk_compute_spr_wm()
2541 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,  in ilk_compute_cur_wm()  argument
2547 	if (!intel_wm_plane_visible(cstate, pstate))  in ilk_compute_cur_wm()
2552 	return ilk_wm_method2(cstate->pixel_rate,  in ilk_compute_cur_wm()
2553 			      cstate->base.adjusted_mode.crtc_htotal,  in ilk_compute_cur_wm()
2558 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,  in ilk_compute_fbc_wm()  argument
2564 	if (!intel_wm_plane_visible(cstate, pstate))  in ilk_compute_fbc_wm()
2739 				 struct intel_crtc_state *cstate,  in ilk_compute_wm_level()  argument
2757 		result->pri_val = ilk_compute_pri_wm(cstate, pristate,  in ilk_compute_wm_level()
2759 		result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);  in ilk_compute_wm_level()
2763 		result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);  in ilk_compute_wm_level()
2766 		result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);  in ilk_compute_wm_level()
2772 hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)  in hsw_compute_linetime_wm()  argument
2775 		to_intel_atomic_state(cstate->base.state);  in hsw_compute_linetime_wm()
2777 		&cstate->base.adjusted_mode;  in hsw_compute_linetime_wm()
2780 	if (!cstate->base.active)  in hsw_compute_linetime_wm()
3051 static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)  in ilk_compute_pipe_wm()  argument
3053 	struct drm_atomic_state *state = cstate->base.state;  in ilk_compute_pipe_wm()
3054 	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);  in ilk_compute_pipe_wm()
3066 	pipe_wm = &cstate->wm.ilk.optimal;  in ilk_compute_pipe_wm()
3068 	drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, &cstate->base) {  in ilk_compute_pipe_wm()
3079 	pipe_wm->pipe_enabled = cstate->base.active;  in ilk_compute_pipe_wm()
3098 	ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,  in ilk_compute_pipe_wm()
3102 		pipe_wm->linetime = hsw_compute_linetime_wm(cstate);  in ilk_compute_pipe_wm()
3112 		ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,  in ilk_compute_pipe_wm()
3708 	struct intel_crtc_state *cstate;  in intel_can_enable_sagv()  local
3737 	cstate = to_intel_crtc_state(crtc->base.state);  in intel_can_enable_sagv()
3744 			&cstate->wm.skl.optimal.planes[plane->id];  in intel_can_enable_sagv()
3775 				       const struct intel_crtc_state *cstate,  in intel_get_ddb_size()  argument
3789 	adjusted_mode = &cstate->base.adjusted_mode;  in intel_get_ddb_size()
3807 				   const struct intel_crtc_state *cstate,  in skl_ddb_get_pipe_allocation_limits()  argument
3813 	struct drm_atomic_state *state = cstate->base.state;  in skl_ddb_get_pipe_allocation_limits()
3816 	struct drm_crtc *for_crtc = cstate->base.crtc;  in skl_ddb_get_pipe_allocation_limits()
3820 	if (WARN_ON(!state) || !cstate->base.active) {  in skl_ddb_get_pipe_allocation_limits()
3832 	ddb_size = intel_get_ddb_size(dev_priv, cstate, total_data_rate,  in skl_ddb_get_pipe_allocation_limits()
3968 skl_plane_downscale_amount(const struct intel_crtc_state *cstate,  in skl_plane_downscale_amount()  argument
3976 	if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))  in skl_plane_downscale_amount()
4043 				  struct intel_crtc_state *cstate)  in skl_check_pipe_max_pixel_rate()  argument
4046 	struct drm_crtc_state *crtc_state = &cstate->base;  in skl_check_pipe_max_pixel_rate()
4056 	if (!cstate->base.enable)  in skl_check_pipe_max_pixel_rate()
4064 		if (!intel_wm_plane_visible(cstate,  in skl_check_pipe_max_pixel_rate()
4072 		plane_downscale = skl_plane_downscale_amount(cstate,  in skl_check_pipe_max_pixel_rate()
4081 	pipe_downscale = skl_pipe_downscale_amount(cstate);  in skl_check_pipe_max_pixel_rate()
4102 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,  in skl_plane_relative_data_rate()  argument
4141 	down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);  in skl_plane_relative_data_rate()
4156 	struct drm_crtc_state *cstate = &intel_cstate->base;  in skl_get_total_relative_data_rate()  local
4157 	struct drm_atomic_state *state = cstate->state;  in skl_get_total_relative_data_rate()
4166 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {  in skl_get_total_relative_data_rate()
4252 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,  in skl_ddb_calc_min()  argument
4258 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {  in skl_ddb_calc_min()
4275 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,  in skl_allocate_pipe_ddb()  argument
4278 	struct drm_atomic_state *state = cstate->base.state;  in skl_allocate_pipe_ddb()
4279 	struct drm_crtc *crtc = cstate->base.crtc;  in skl_allocate_pipe_ddb()
4283 	struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;  in skl_allocate_pipe_ddb()
4301 	if (!cstate->base.active) {  in skl_allocate_pipe_ddb()
4306 	total_data_rate = skl_get_total_relative_data_rate(cstate,  in skl_allocate_pipe_ddb()
4309 	skl_ddb_get_pipe_allocation_limits(dev, cstate, total_data_rate, ddb,  in skl_allocate_pipe_ddb()
4315 	skl_ddb_calc_min(cstate, num_active, minimum, uv_minimum);  in skl_allocate_pipe_ddb()
4438 intel_get_linetime_us(struct intel_crtc_state *cstate)  in intel_get_linetime_us()  argument
4444 	if (!cstate->base.active)  in intel_get_linetime_us()
4447 	pixel_rate = cstate->pixel_rate;  in intel_get_linetime_us()
4452 	crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;  in intel_get_linetime_us()
4459 skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,  in skl_adjusted_plane_pixel_rate()  argument
4466 	if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))  in skl_adjusted_plane_pixel_rate()
4473 	adjusted_pixel_rate = cstate->pixel_rate;  in skl_adjusted_plane_pixel_rate()
4474 	downscale_amount = skl_plane_downscale_amount(cstate, pstate);  in skl_adjusted_plane_pixel_rate()
4482 			    struct intel_crtc_state *cstate,  in skl_compute_plane_wm_params()  argument
4491 		to_intel_atomic_state(cstate->base.state);  in skl_compute_plane_wm_params()
4494 	if (!intel_wm_plane_visible(cstate, intel_pstate))  in skl_compute_plane_wm_params()
4527 	wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,  in skl_compute_plane_wm_params()
4583 					intel_get_linetime_us(cstate));  in skl_compute_plane_wm_params()
4589 				struct intel_crtc_state *cstate,  in skl_compute_plane_wm()  argument
4603 		to_intel_atomic_state(cstate->base.state);  in skl_compute_plane_wm()
4608 	    !intel_wm_plane_visible(cstate, intel_pstate)) {  in skl_compute_plane_wm()
4625 				 cstate->base.adjusted_mode.crtc_htotal,  in skl_compute_plane_wm()
4632 		if ((wp->cpp * cstate->base.adjusted_mode.crtc_htotal /  in skl_compute_plane_wm()
4740 		      struct intel_crtc_state *cstate,  in skl_compute_wm_levels()  argument
4746 	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);  in skl_compute_wm_levels()
4774 					   cstate,  in skl_compute_wm_levels()
4792 skl_compute_linetime_wm(struct intel_crtc_state *cstate)  in skl_compute_linetime_wm()  argument
4794 	struct drm_atomic_state *state = cstate->base.state;  in skl_compute_linetime_wm()
4799 	linetime_us = intel_get_linetime_us(cstate);  in skl_compute_linetime_wm()
4814 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,  in skl_compute_transition_wm()  argument
4820 	struct drm_device *dev = cstate->base.crtc->dev;  in skl_compute_transition_wm()
4826 	if (!cstate->base.active)  in skl_compute_transition_wm()
4869 static int skl_build_pipe_wm(struct intel_crtc_state *cstate,  in skl_build_pipe_wm()  argument
4873 	struct drm_device *dev = cstate->base.crtc->dev;  in skl_build_pipe_wm()
4874 	struct drm_crtc_state *crtc_state = &cstate->base;  in skl_build_pipe_wm()
4892 		enum pipe pipe = to_intel_crtc(cstate->base.crtc)->pipe;  in skl_build_pipe_wm()
4898 		ret = skl_compute_plane_wm_params(dev_priv, cstate,  in skl_build_pipe_wm()
4903 		ret = skl_compute_wm_levels(dev_priv, ddb, cstate,  in skl_build_pipe_wm()
4908 		skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],  in skl_build_pipe_wm()
4916 			ret = skl_compute_plane_wm_params(dev_priv, cstate,  in skl_build_pipe_wm()
4922 			ret = skl_compute_wm_levels(dev_priv, ddb, cstate,  in skl_build_pipe_wm()
4930 	pipe_wm->linetime = skl_compute_linetime_wm(cstate);  in skl_build_pipe_wm()
5053 static int skl_update_pipe_wm(struct drm_crtc_state *cstate,  in skl_update_pipe_wm()  argument
5059 	struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);  in skl_update_pipe_wm()
5078 	struct drm_crtc_state *cstate;  in pipes_modified()  local
5081 	for_each_new_crtc_in_state(state, crtc, cstate, i)  in pipes_modified()
5088 skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)  in skl_ddb_add_affected_planes()  argument
5090 	struct drm_atomic_state *state = cstate->base.state;  in skl_ddb_add_affected_planes()
5092 	struct drm_crtc *crtc = cstate->base.crtc;  in skl_ddb_add_affected_planes()
5102 	drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {  in skl_ddb_add_affected_planes()
5126 	struct intel_crtc_state *cstate;  in skl_compute_ddb()  local
5131 	for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {  in skl_compute_ddb()
5132 		ret = skl_allocate_pipe_ddb(cstate, ddb);  in skl_compute_ddb()
5136 		ret = skl_ddb_add_affected_planes(cstate);  in skl_compute_ddb()
5163 	const struct drm_crtc_state *cstate;  in skl_print_wm_changes()  local
5169 	for_each_new_crtc_in_state(state, crtc, cstate, i) {  in skl_print_wm_changes()
5198 	const struct drm_crtc_state *cstate;  in skl_ddb_add_affected_pipes()  local
5219 	for_each_new_crtc_in_state(state, crtc, cstate, i)  in skl_ddb_add_affected_pipes()
5272 		struct intel_crtc_state *cstate;  in skl_ddb_add_affected_pipes()  local
5274 		cstate = intel_atomic_get_crtc_state(state, intel_crtc);  in skl_ddb_add_affected_pipes()
5275 		if (IS_ERR(cstate))  in skl_ddb_add_affected_pipes()
5276 			return PTR_ERR(cstate);  in skl_ddb_add_affected_pipes()
5286 	struct drm_crtc_state *cstate;  in skl_compute_wm()  local
5314 	for_each_new_crtc_in_state(state, crtc, cstate, i) {  in skl_compute_wm()
5316 			to_intel_crtc_state(cstate);  in skl_compute_wm()
5321 		ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,  in skl_compute_wm()
5342 				      struct intel_crtc_state *cstate)  in skl_atomic_update_crtc_wm()  argument
5344 	struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);  in skl_atomic_update_crtc_wm()
5346 	struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;  in skl_atomic_update_crtc_wm()
5367 			   struct intel_crtc_state *cstate)  in skl_initial_wm()  argument
5369 	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);  in skl_initial_wm()
5381 	if (cstate->base.active_changed)  in skl_initial_wm()
5382 		skl_atomic_update_crtc_wm(state, cstate);  in skl_initial_wm()
5441 				   struct intel_crtc_state *cstate)  in ilk_initial_watermarks()  argument
5443 	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);  in ilk_initial_watermarks()
5444 	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);  in ilk_initial_watermarks()
5447 	intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;  in ilk_initial_watermarks()
5453 				    struct intel_crtc_state *cstate)  in ilk_optimize_watermarks()  argument
5455 	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);  in ilk_optimize_watermarks()
5456 	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);  in ilk_optimize_watermarks()
5459 	if (cstate->wm.need_postvbl_update) {  in ilk_optimize_watermarks()
5460 		intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;  in ilk_optimize_watermarks()
5520 	struct intel_crtc_state *cstate;  in skl_wm_get_hw_state()  local
5525 		cstate = to_intel_crtc_state(crtc->state);  in skl_wm_get_hw_state()
5527 		skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);  in skl_wm_get_hw_state()
5552 	struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);  in ilk_pipe_wm_get_hw_state()  local
5553 	struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;  in ilk_pipe_wm_get_hw_state()