Lines Matching refs:engine
168 struct intel_engine_cs *engine,
172 struct intel_engine_cs *engine,
185 static inline bool need_preempt(const struct intel_engine_cs *engine, in need_preempt() argument
189 return (intel_engine_has_preemption(engine) && in need_preempt()
222 struct intel_engine_cs *engine, in intel_lr_context_descriptor_update() argument
247 desc |= (u64)engine->instance << GEN11_ENGINE_INSTANCE_SHIFT; in intel_lr_context_descriptor_update()
252 desc |= (u64)engine->class << GEN11_ENGINE_CLASS_SHIFT; in intel_lr_context_descriptor_update()
263 lookup_priolist(struct intel_engine_cs *engine, int prio) in lookup_priolist() argument
265 struct intel_engine_execlists * const execlists = &engine->execlists; in lookup_priolist()
293 p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC); in lookup_priolist()
325 static void __unwind_incomplete_requests(struct intel_engine_cs *engine) in __unwind_incomplete_requests() argument
331 lockdep_assert_held(&engine->timeline.lock); in __unwind_incomplete_requests()
334 &engine->timeline.requests, in __unwind_incomplete_requests()
345 p = lookup_priolist(engine, last_prio); in __unwind_incomplete_requests()
356 struct intel_engine_cs *engine = in execlists_unwind_incomplete_requests() local
357 container_of(execlists, typeof(*engine), execlists); in execlists_unwind_incomplete_requests()
360 spin_lock_irqsave(&engine->timeline.lock, flags); in execlists_unwind_incomplete_requests()
362 __unwind_incomplete_requests(engine); in execlists_unwind_incomplete_requests()
364 spin_unlock_irqrestore(&engine->timeline.lock, flags); in execlists_unwind_incomplete_requests()
377 atomic_notifier_call_chain(&rq->engine->context_status_notifier, in execlists_context_status_change()
398 intel_engine_context_in(rq->engine); in execlists_context_schedule_in()
404 intel_engine_context_out(rq->engine); in execlists_context_schedule_out()
449 static void execlists_submit_ports(struct intel_engine_cs *engine) in execlists_submit_ports() argument
451 struct intel_engine_execlists *execlists = &engine->execlists; in execlists_submit_ports()
463 GEM_BUG_ON(!engine->i915->gt.awake); in execlists_submit_ports()
486 engine->name, n, in execlists_submit_ports()
490 intel_engine_get_seqno(engine), in execlists_submit_ports()
535 static void inject_preempt_context(struct intel_engine_cs *engine) in inject_preempt_context() argument
537 struct intel_engine_execlists *execlists = &engine->execlists; in inject_preempt_context()
539 to_intel_context(engine->i915->preempt_context, engine); in inject_preempt_context()
554 GEM_TRACE("%s\n", engine->name); in inject_preempt_context()
581 static void execlists_dequeue(struct intel_engine_cs *engine) in execlists_dequeue() argument
583 struct intel_engine_execlists * const execlists = &engine->execlists; in execlists_dequeue()
634 if (need_preempt(engine, last, execlists->queue_priority)) { in execlists_dequeue()
635 inject_preempt_context(engine); in execlists_dequeue()
736 kmem_cache_free(engine->i915->priorities, p); in execlists_dequeue()
761 execlists_submit_ports(engine); in execlists_dequeue()
773 GEM_BUG_ON(execlists_is_active(&engine->execlists, in execlists_dequeue()
775 !port_isset(engine->execlists.port)); in execlists_dequeue()
788 rq->engine->name, in execlists_cancel_port_requests()
792 intel_engine_get_seqno(rq->engine)); in execlists_cancel_port_requests()
829 static void execlists_cancel_requests(struct intel_engine_cs *engine) in execlists_cancel_requests() argument
831 struct intel_engine_execlists * const execlists = &engine->execlists; in execlists_cancel_requests()
837 engine->name, intel_engine_get_seqno(engine)); in execlists_cancel_requests()
853 spin_lock_irqsave(&engine->timeline.lock, flags); in execlists_cancel_requests()
860 list_for_each_entry(rq, &engine->timeline.requests, link) { in execlists_cancel_requests()
880 kmem_cache_free(engine->i915->priorities, p); in execlists_cancel_requests()
892 spin_unlock_irqrestore(&engine->timeline.lock, flags); in execlists_cancel_requests()
901 static void process_csb(struct intel_engine_cs *engine) in process_csb() argument
903 struct intel_engine_execlists * const execlists = &engine->execlists; in process_csb()
920 GEM_TRACE("%s cs-irq head=%d, tail=%d\n", engine->name, head, tail); in process_csb()
961 engine->name, head, in process_csb()
982 GEM_TRACE("%s preempt-idle\n", engine->name); in process_csb()
997 engine->name, in process_csb()
1002 intel_engine_get_seqno(engine), in process_csb()
1037 engine->name, port->context_id); in process_csb()
1052 static void __execlists_submission_tasklet(struct intel_engine_cs *const engine) in __execlists_submission_tasklet() argument
1054 lockdep_assert_held(&engine->timeline.lock); in __execlists_submission_tasklet()
1056 process_csb(engine); in __execlists_submission_tasklet()
1057 if (!execlists_is_active(&engine->execlists, EXECLISTS_ACTIVE_PREEMPT)) in __execlists_submission_tasklet()
1058 execlists_dequeue(engine); in __execlists_submission_tasklet()
1067 struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; in execlists_submission_tasklet() local
1071 engine->name, in execlists_submission_tasklet()
1072 engine->i915->gt.awake, in execlists_submission_tasklet()
1073 engine->execlists.active); in execlists_submission_tasklet()
1075 spin_lock_irqsave(&engine->timeline.lock, flags); in execlists_submission_tasklet()
1076 __execlists_submission_tasklet(engine); in execlists_submission_tasklet()
1077 spin_unlock_irqrestore(&engine->timeline.lock, flags); in execlists_submission_tasklet()
1080 static void queue_request(struct intel_engine_cs *engine, in queue_request() argument
1085 &lookup_priolist(engine, prio)->requests); in queue_request()
1088 static void __update_queue(struct intel_engine_cs *engine, int prio) in __update_queue() argument
1090 engine->execlists.queue_priority = prio; in __update_queue()
1093 static void __submit_queue_imm(struct intel_engine_cs *engine) in __submit_queue_imm() argument
1095 struct intel_engine_execlists * const execlists = &engine->execlists; in __submit_queue_imm()
1101 __execlists_submission_tasklet(engine); in __submit_queue_imm()
1106 static void submit_queue(struct intel_engine_cs *engine, int prio) in submit_queue() argument
1108 if (prio > engine->execlists.queue_priority) { in submit_queue()
1109 __update_queue(engine, prio); in submit_queue()
1110 __submit_queue_imm(engine); in submit_queue()
1116 struct intel_engine_cs *engine = request->engine; in execlists_submit_request() local
1120 spin_lock_irqsave(&engine->timeline.lock, flags); in execlists_submit_request()
1122 queue_request(engine, &request->sched, rq_prio(request)); in execlists_submit_request()
1124 GEM_BUG_ON(RB_EMPTY_ROOT(&engine->execlists.queue.rb_root)); in execlists_submit_request()
1127 submit_queue(engine, rq_prio(request)); in execlists_submit_request()
1129 spin_unlock_irqrestore(&engine->timeline.lock, flags); in execlists_submit_request()
1140 struct intel_engine_cs *engine = sched_to_request(node)->engine; in sched_lock_engine() local
1144 if (engine != locked) { in sched_lock_engine()
1146 spin_lock(&engine->timeline.lock); in sched_lock_engine()
1149 return engine; in sched_lock_engine()
1156 struct intel_engine_cs *engine, *last; in execlists_schedule() local
1230 engine = request->engine; in execlists_schedule()
1231 spin_lock_irq(&engine->timeline.lock); in execlists_schedule()
1239 engine = sched_lock_engine(node, engine); in execlists_schedule()
1246 if (last != engine) { in execlists_schedule()
1247 pl = lookup_priolist(engine, prio); in execlists_schedule()
1248 last = engine; in execlists_schedule()
1254 if (prio > engine->execlists.queue_priority && in execlists_schedule()
1257 __update_queue(engine, prio); in execlists_schedule()
1258 tasklet_hi_schedule(&engine->execlists.tasklet); in execlists_schedule()
1262 spin_unlock_irq(&engine->timeline.lock); in execlists_schedule()
1313 __execlists_context_pin(struct intel_engine_cs *engine, in __execlists_context_pin() argument
1320 ret = execlists_context_deferred_alloc(ctx, engine, ce); in __execlists_context_pin()
1339 intel_lr_context_descriptor_update(ctx, engine, ce); in __execlists_context_pin()
1366 execlists_context_pin(struct intel_engine_cs *engine, in execlists_context_pin() argument
1369 struct intel_context *ce = to_intel_context(ctx, engine); in execlists_context_pin()
1379 return __execlists_context_pin(engine, ctx, ce); in execlists_context_pin()
1426 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) in gen8_emit_flush_coherentl3_wa() argument
1430 *batch++ = i915_ggtt_offset(engine->scratch) + 256; in gen8_emit_flush_coherentl3_wa()
1444 *batch++ = i915_ggtt_offset(engine->scratch) + 256; in gen8_emit_flush_coherentl3_wa()
1465 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) in gen8_init_indirectctx_bb() argument
1471 if (IS_BROADWELL(engine->i915)) in gen8_init_indirectctx_bb()
1472 batch = gen8_emit_flush_coherentl3_wa(engine, batch); in gen8_init_indirectctx_bb()
1481 i915_ggtt_offset(engine->scratch) + in gen8_init_indirectctx_bb()
1518 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) in gen9_init_indirectctx_bb() argument
1546 batch = gen8_emit_flush_coherentl3_wa(engine, batch); in gen9_init_indirectctx_bb()
1552 if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) { in gen9_init_indirectctx_bb()
1558 i915_ggtt_offset(engine->scratch) in gen9_init_indirectctx_bb()
1563 if (HAS_POOLED_EU(engine->i915)) { in gen9_init_indirectctx_bb()
1595 gen10_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) in gen10_init_indirectctx_bb() argument
1630 static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) in lrc_setup_wa_ctx() argument
1636 obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE); in lrc_setup_wa_ctx()
1640 vma = i915_vma_instance(obj, &engine->i915->ggtt.vm, NULL); in lrc_setup_wa_ctx()
1650 engine->wa_ctx.vma = vma; in lrc_setup_wa_ctx()
1658 static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine) in lrc_destroy_wa_ctx() argument
1660 i915_vma_unpin_and_release(&engine->wa_ctx.vma); in lrc_destroy_wa_ctx()
1663 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1665 static int intel_init_workaround_bb(struct intel_engine_cs *engine) in intel_init_workaround_bb() argument
1667 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; in intel_init_workaround_bb()
1676 if (GEM_WARN_ON(engine->id != RCS)) in intel_init_workaround_bb()
1679 switch (INTEL_GEN(engine->i915)) { in intel_init_workaround_bb()
1695 MISSING_CASE(INTEL_GEN(engine->i915)); in intel_init_workaround_bb()
1699 ret = lrc_setup_wa_ctx(engine); in intel_init_workaround_bb()
1721 batch_ptr = wa_bb_fn[i](engine, batch_ptr); in intel_init_workaround_bb()
1729 lrc_destroy_wa_ctx(engine); in intel_init_workaround_bb()
1734 static void enable_execlists(struct intel_engine_cs *engine) in enable_execlists() argument
1736 struct drm_i915_private *dev_priv = engine->i915; in enable_execlists()
1738 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); in enable_execlists()
1749 I915_WRITE(RING_MODE_GEN7(engine), in enable_execlists()
1752 I915_WRITE(RING_MODE_GEN7(engine), in enable_execlists()
1755 I915_WRITE(RING_MI_MODE(engine->mmio_base), in enable_execlists()
1758 I915_WRITE(RING_HWS_PGA(engine->mmio_base), in enable_execlists()
1759 engine->status_page.ggtt_offset); in enable_execlists()
1760 POSTING_READ(RING_HWS_PGA(engine->mmio_base)); in enable_execlists()
1763 static bool unexpected_starting_state(struct intel_engine_cs *engine) in unexpected_starting_state() argument
1765 struct drm_i915_private *dev_priv = engine->i915; in unexpected_starting_state()
1768 if (I915_READ(RING_MI_MODE(engine->mmio_base)) & STOP_RING) { in unexpected_starting_state()
1776 static int gen8_init_common_ring(struct intel_engine_cs *engine) in gen8_init_common_ring() argument
1780 ret = intel_mocs_init_engine(engine); in gen8_init_common_ring()
1784 intel_engine_reset_breadcrumbs(engine); in gen8_init_common_ring()
1786 if (GEM_SHOW_DEBUG() && unexpected_starting_state(engine)) { in gen8_init_common_ring()
1789 intel_engine_dump(engine, &p, NULL); in gen8_init_common_ring()
1792 enable_execlists(engine); in gen8_init_common_ring()
1797 static int gen8_init_render_ring(struct intel_engine_cs *engine) in gen8_init_render_ring() argument
1799 struct drm_i915_private *dev_priv = engine->i915; in gen8_init_render_ring()
1802 ret = gen8_init_common_ring(engine); in gen8_init_render_ring()
1806 intel_whitelist_workarounds_apply(engine); in gen8_init_render_ring()
1821 static int gen9_init_render_ring(struct intel_engine_cs *engine) in gen9_init_render_ring() argument
1825 ret = gen8_init_common_ring(engine); in gen9_init_render_ring()
1829 intel_whitelist_workarounds_apply(engine); in gen9_init_render_ring()
1835 execlists_reset_prepare(struct intel_engine_cs *engine) in execlists_reset_prepare() argument
1837 struct intel_engine_execlists * const execlists = &engine->execlists; in execlists_reset_prepare()
1841 GEM_TRACE("%s\n", engine->name); in execlists_reset_prepare()
1854 spin_lock_irqsave(&engine->timeline.lock, flags); in execlists_reset_prepare()
1863 process_csb(engine); in execlists_reset_prepare()
1877 intel_engine_stop_cs(engine); in execlists_reset_prepare()
1880 &engine->timeline.requests, in execlists_reset_prepare()
1890 spin_unlock_irqrestore(&engine->timeline.lock, flags); in execlists_reset_prepare()
1895 static void execlists_reset(struct intel_engine_cs *engine, in execlists_reset() argument
1898 struct intel_engine_execlists * const execlists = &engine->execlists; in execlists_reset()
1903 engine->name, request ? request->global_seqno : 0, in execlists_reset()
1904 intel_engine_get_seqno(engine)); in execlists_reset()
1906 spin_lock_irqsave(&engine->timeline.lock, flags); in execlists_reset()
1920 __unwind_incomplete_requests(engine); in execlists_reset()
1923 reset_csb_pointers(&engine->execlists); in execlists_reset()
1925 spin_unlock_irqrestore(&engine->timeline.lock, flags); in execlists_reset()
1950 if (engine->pinned_default_state) { in execlists_reset()
1952 engine->pinned_default_state + LRC_STATE_PN * PAGE_SIZE, in execlists_reset()
1953 engine->context_size - PAGE_SIZE); in execlists_reset()
1956 request->gem_context, engine, request->ring); in execlists_reset()
1970 static void execlists_reset_finish(struct intel_engine_cs *engine) in execlists_reset_finish() argument
1972 struct intel_engine_execlists * const execlists = &engine->execlists; in execlists_reset_finish()
1989 GEM_TRACE("%s\n", engine->name); in execlists_reset_finish()
1995 struct intel_engine_cs *engine = rq->engine; in intel_logical_ring_emit_pdps() local
2008 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i)); in intel_logical_ring_emit_pdps()
2010 *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i)); in intel_logical_ring_emit_pdps()
2034 (intel_engine_flag(rq->engine) & rq->gem_context->ppgtt->pd_dirty_rings) && in gen8_emit_bb_start()
2041 rq->gem_context->ppgtt->pd_dirty_rings &= ~intel_engine_flag(rq->engine); in gen8_emit_bb_start()
2081 static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) in gen8_logical_ring_enable_irq() argument
2083 struct drm_i915_private *dev_priv = engine->i915; in gen8_logical_ring_enable_irq()
2084 I915_WRITE_IMR(engine, in gen8_logical_ring_enable_irq()
2085 ~(engine->irq_enable_mask | engine->irq_keep_mask)); in gen8_logical_ring_enable_irq()
2086 POSTING_READ_FW(RING_IMR(engine->mmio_base)); in gen8_logical_ring_enable_irq()
2089 static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) in gen8_logical_ring_disable_irq() argument
2091 struct drm_i915_private *dev_priv = engine->i915; in gen8_logical_ring_disable_irq()
2092 I915_WRITE_IMR(engine, ~engine->irq_keep_mask); in gen8_logical_ring_disable_irq()
2114 if (request->engine->id == VCS) in gen8_emit_flush()
2130 struct intel_engine_cs *engine = request->engine; in gen8_emit_flush_render() local
2132 i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; in gen8_emit_flush_render()
2216 intel_hws_seqno_address(request->engine)); in gen8_emit_breadcrumb()
2232 intel_hws_seqno_address(request->engine)); in gen8_emit_breadcrumb_rcs()
2265 void intel_logical_ring_cleanup(struct intel_engine_cs *engine) in intel_logical_ring_cleanup() argument
2274 &engine->execlists.tasklet.state))) in intel_logical_ring_cleanup()
2275 tasklet_kill(&engine->execlists.tasklet); in intel_logical_ring_cleanup()
2277 dev_priv = engine->i915; in intel_logical_ring_cleanup()
2279 if (engine->buffer) { in intel_logical_ring_cleanup()
2280 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); in intel_logical_ring_cleanup()
2283 if (engine->cleanup) in intel_logical_ring_cleanup()
2284 engine->cleanup(engine); in intel_logical_ring_cleanup()
2286 intel_engine_cleanup_common(engine); in intel_logical_ring_cleanup()
2288 lrc_destroy_wa_ctx(engine); in intel_logical_ring_cleanup()
2290 engine->i915 = NULL; in intel_logical_ring_cleanup()
2291 dev_priv->engine[engine->id] = NULL; in intel_logical_ring_cleanup()
2292 kfree(engine); in intel_logical_ring_cleanup()
2295 void intel_execlists_set_default_submission(struct intel_engine_cs *engine) in intel_execlists_set_default_submission() argument
2297 engine->submit_request = execlists_submit_request; in intel_execlists_set_default_submission()
2298 engine->cancel_requests = execlists_cancel_requests; in intel_execlists_set_default_submission()
2299 engine->schedule = execlists_schedule; in intel_execlists_set_default_submission()
2300 engine->execlists.tasklet.func = execlists_submission_tasklet; in intel_execlists_set_default_submission()
2302 engine->reset.prepare = execlists_reset_prepare; in intel_execlists_set_default_submission()
2304 engine->park = NULL; in intel_execlists_set_default_submission()
2305 engine->unpark = NULL; in intel_execlists_set_default_submission()
2307 engine->flags |= I915_ENGINE_SUPPORTS_STATS; in intel_execlists_set_default_submission()
2308 if (engine->i915->preempt_context) in intel_execlists_set_default_submission()
2309 engine->flags |= I915_ENGINE_HAS_PREEMPTION; in intel_execlists_set_default_submission()
2311 engine->i915->caps.scheduler = in intel_execlists_set_default_submission()
2314 if (intel_engine_has_preemption(engine)) in intel_execlists_set_default_submission()
2315 engine->i915->caps.scheduler |= I915_SCHEDULER_CAP_PREEMPTION; in intel_execlists_set_default_submission()
2319 logical_ring_default_vfuncs(struct intel_engine_cs *engine) in logical_ring_default_vfuncs() argument
2322 engine->init_hw = gen8_init_common_ring; in logical_ring_default_vfuncs()
2324 engine->reset.prepare = execlists_reset_prepare; in logical_ring_default_vfuncs()
2325 engine->reset.reset = execlists_reset; in logical_ring_default_vfuncs()
2326 engine->reset.finish = execlists_reset_finish; in logical_ring_default_vfuncs()
2328 engine->context_pin = execlists_context_pin; in logical_ring_default_vfuncs()
2329 engine->request_alloc = execlists_request_alloc; in logical_ring_default_vfuncs()
2331 engine->emit_flush = gen8_emit_flush; in logical_ring_default_vfuncs()
2332 engine->emit_breadcrumb = gen8_emit_breadcrumb; in logical_ring_default_vfuncs()
2333 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz; in logical_ring_default_vfuncs()
2335 engine->set_default_submission = intel_execlists_set_default_submission; in logical_ring_default_vfuncs()
2337 if (INTEL_GEN(engine->i915) < 11) { in logical_ring_default_vfuncs()
2338 engine->irq_enable = gen8_logical_ring_enable_irq; in logical_ring_default_vfuncs()
2339 engine->irq_disable = gen8_logical_ring_disable_irq; in logical_ring_default_vfuncs()
2348 engine->emit_bb_start = gen8_emit_bb_start; in logical_ring_default_vfuncs()
2352 logical_ring_default_irqs(struct intel_engine_cs *engine) in logical_ring_default_irqs() argument
2356 if (INTEL_GEN(engine->i915) < 11) { in logical_ring_default_irqs()
2365 shift = irq_shifts[engine->id]; in logical_ring_default_irqs()
2368 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; in logical_ring_default_irqs()
2369 engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; in logical_ring_default_irqs()
2373 logical_ring_setup(struct intel_engine_cs *engine) in logical_ring_setup() argument
2375 intel_engine_setup_common(engine); in logical_ring_setup()
2378 engine->buffer = NULL; in logical_ring_setup()
2380 tasklet_init(&engine->execlists.tasklet, in logical_ring_setup()
2381 execlists_submission_tasklet, (unsigned long)engine); in logical_ring_setup()
2383 logical_ring_default_vfuncs(engine); in logical_ring_setup()
2384 logical_ring_default_irqs(engine); in logical_ring_setup()
2393 static int logical_ring_init(struct intel_engine_cs *engine) in logical_ring_init() argument
2395 struct drm_i915_private *i915 = engine->i915; in logical_ring_init()
2396 struct intel_engine_execlists * const execlists = &engine->execlists; in logical_ring_init()
2399 ret = intel_engine_init_common(engine); in logical_ring_init()
2405 i915_mmio_reg_offset(RING_EXECLIST_SQ_CONTENTS(engine)); in logical_ring_init()
2407 i915_mmio_reg_offset(RING_EXECLIST_CONTROL(engine)); in logical_ring_init()
2410 i915_mmio_reg_offset(RING_ELSP(engine)); in logical_ring_init()
2416 to_intel_context(i915->preempt_context, engine); in logical_ring_init()
2423 i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); in logical_ring_init()
2426 (i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0))); in logical_ring_init()
2434 &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX]; in logical_ring_init()
2437 &engine->status_page.page_addr[intel_hws_csb_write_index(i915)]; in logical_ring_init()
2445 intel_logical_ring_cleanup(engine); in logical_ring_init()
2449 int logical_render_ring_init(struct intel_engine_cs *engine) in logical_render_ring_init() argument
2451 struct drm_i915_private *dev_priv = engine->i915; in logical_render_ring_init()
2454 logical_ring_setup(engine); in logical_render_ring_init()
2457 engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; in logical_render_ring_init()
2461 engine->init_hw = gen9_init_render_ring; in logical_render_ring_init()
2463 engine->init_hw = gen8_init_render_ring; in logical_render_ring_init()
2464 engine->init_context = gen8_init_rcs_context; in logical_render_ring_init()
2465 engine->emit_flush = gen8_emit_flush_render; in logical_render_ring_init()
2466 engine->emit_breadcrumb = gen8_emit_breadcrumb_rcs; in logical_render_ring_init()
2467 engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_rcs_sz; in logical_render_ring_init()
2469 ret = intel_engine_create_scratch(engine, PAGE_SIZE); in logical_render_ring_init()
2473 ret = intel_init_workaround_bb(engine); in logical_render_ring_init()
2484 return logical_ring_init(engine); in logical_render_ring_init()
2487 int logical_xcs_ring_init(struct intel_engine_cs *engine) in logical_xcs_ring_init() argument
2489 logical_ring_setup(engine); in logical_xcs_ring_init()
2491 return logical_ring_init(engine); in logical_xcs_ring_init()
2537 static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) in intel_lr_indirect_ctx_offset() argument
2541 switch (INTEL_GEN(engine->i915)) { in intel_lr_indirect_ctx_offset()
2543 MISSING_CASE(INTEL_GEN(engine->i915)); in intel_lr_indirect_ctx_offset()
2568 struct intel_engine_cs *engine, in execlists_init_reg_state() argument
2571 struct drm_i915_private *dev_priv = engine->i915; in execlists_init_reg_state()
2573 u32 base = engine->mmio_base; in execlists_init_reg_state()
2574 bool rcs = engine->class == RENDER_CLASS; in execlists_init_reg_state()
2586 CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine), in execlists_init_reg_state()
2604 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; in execlists_init_reg_state()
2617 intel_lr_indirect_ctx_offset(engine) << 6; in execlists_init_reg_state()
2633 CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0); in execlists_init_reg_state()
2634 CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0); in execlists_init_reg_state()
2635 CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0); in execlists_init_reg_state()
2636 CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0); in execlists_init_reg_state()
2637 CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0); in execlists_init_reg_state()
2638 CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0); in execlists_init_reg_state()
2639 CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0); in execlists_init_reg_state()
2640 CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0); in execlists_init_reg_state()
2655 i915_oa_init_reg_state(engine, ctx, regs); in execlists_init_reg_state()
2662 struct intel_engine_cs *engine, in populate_lr_context() argument
2683 if (engine->default_state) { in populate_lr_context()
2692 defaults = i915_gem_object_pin_map(engine->default_state, in populate_lr_context()
2699 memcpy(vaddr + start, defaults + start, engine->context_size); in populate_lr_context()
2700 i915_gem_object_unpin_map(engine->default_state); in populate_lr_context()
2706 execlists_init_reg_state(regs, ctx, engine, ring); in populate_lr_context()
2707 if (!engine->default_state) in populate_lr_context()
2710 if (ctx == ctx->i915->preempt_context && INTEL_GEN(engine->i915) < 11) in populate_lr_context()
2721 struct intel_engine_cs *engine, in execlists_context_deferred_alloc() argument
2734 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE); in execlists_context_deferred_alloc()
2758 ring = intel_engine_create_ring(engine, timeline, ctx->ring_size); in execlists_context_deferred_alloc()
2765 ret = populate_lr_context(ctx, ctx_obj, engine, ring); in execlists_context_deferred_alloc()
2785 struct intel_engine_cs *engine; in intel_lr_context_resume() local
2800 for_each_engine(engine, dev_priv, id) { in intel_lr_context_resume()
2802 to_intel_context(ctx, engine); in intel_lr_context_resume()