Lines Matching refs:cpu_transcoder
64 enum transcoder cpu_transcoder) in assert_hdmi_transcoder_func_disabled() argument
66 WARN(I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)) & in assert_hdmi_transcoder_func_disabled()
132 enum transcoder cpu_transcoder, in hsw_dip_data_reg() argument
138 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); in hsw_dip_data_reg()
140 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); in hsw_dip_data_reg()
142 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); in hsw_dip_data_reg()
144 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); in hsw_dip_data_reg()
391 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; in hsw_write_infoframe() local
392 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); in hsw_write_infoframe()
403 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, in hsw_write_infoframe()
409 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder, in hsw_write_infoframe()
422 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); in hsw_infoframe_enabled()
670 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); in intel_hdmi_set_gcp_infoframe()
847 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); in hsw_set_infoframes()
851 crtc_state->cpu_transcoder); in hsw_set_infoframes()