53 	struct drm_i915_private *dev_priv = to_i915(dev);  in ivb_can_enable_err_int()  local
57 	lockdep_assert_held(&dev_priv->irq_lock);  in ivb_can_enable_err_int()
59 	for_each_pipe(dev_priv, pipe) {  in ivb_can_enable_err_int()
60 		crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in ivb_can_enable_err_int()
71 	struct drm_i915_private *dev_priv = to_i915(dev);  in cpt_can_enable_serr_int()  local
75 	lockdep_assert_held(&dev_priv->irq_lock);  in cpt_can_enable_serr_int()
77 	for_each_pipe(dev_priv, pipe) {  in cpt_can_enable_serr_int()
78 		crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in cpt_can_enable_serr_int()
89 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in i9xx_check_fifo_underruns()  local
93 	lockdep_assert_held(&dev_priv->irq_lock);  in i9xx_check_fifo_underruns()
98 	enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe);  in i9xx_check_fifo_underruns()
102 	trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe);  in i9xx_check_fifo_underruns()
110 	struct drm_i915_private *dev_priv = to_i915(dev);  in i9xx_set_fifo_underrun_reporting()  local
113 	lockdep_assert_held(&dev_priv->irq_lock);  in i9xx_set_fifo_underrun_reporting()
116 		u32 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);  in i9xx_set_fifo_underrun_reporting()
129 	struct drm_i915_private *dev_priv = to_i915(dev);  in ironlake_set_fifo_underrun_reporting()  local
134 		ilk_enable_display_irq(dev_priv, bit);  in ironlake_set_fifo_underrun_reporting()
136 		ilk_disable_display_irq(dev_priv, bit);  in ironlake_set_fifo_underrun_reporting()
141 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in ivybridge_check_fifo_underruns()  local
145 	lockdep_assert_held(&dev_priv->irq_lock);  in ivybridge_check_fifo_underruns()
153 	trace_intel_cpu_fifo_underrun(dev_priv, pipe);  in ivybridge_check_fifo_underruns()
161 	struct drm_i915_private *dev_priv = to_i915(dev);  in ivybridge_set_fifo_underrun_reporting()  local
168 		ilk_enable_display_irq(dev_priv, DE_ERR_INT_IVB);  in ivybridge_set_fifo_underrun_reporting()
170 		ilk_disable_display_irq(dev_priv, DE_ERR_INT_IVB);  in ivybridge_set_fifo_underrun_reporting()
183 	struct drm_i915_private *dev_priv = to_i915(dev);  in broadwell_set_fifo_underrun_reporting()  local
186 		bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);  in broadwell_set_fifo_underrun_reporting()
188 		bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_FIFO_UNDERRUN);  in broadwell_set_fifo_underrun_reporting()
195 	struct drm_i915_private *dev_priv = to_i915(dev);  in ibx_set_fifo_underrun_reporting()  local
200 		ibx_enable_display_interrupt(dev_priv, bit);  in ibx_set_fifo_underrun_reporting()
202 		ibx_disable_display_interrupt(dev_priv, bit);  in ibx_set_fifo_underrun_reporting()
207 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);  in cpt_check_pch_fifo_underruns()  local
211 	lockdep_assert_held(&dev_priv->irq_lock);  in cpt_check_pch_fifo_underruns()
219 	trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);  in cpt_check_pch_fifo_underruns()
228 	struct drm_i915_private *dev_priv = to_i915(dev);  in cpt_set_fifo_underrun_reporting()  local
237 		ibx_enable_display_interrupt(dev_priv, SDE_ERROR_CPT);  in cpt_set_fifo_underrun_reporting()
239 		ibx_disable_display_interrupt(dev_priv, SDE_ERROR_CPT);  in cpt_set_fifo_underrun_reporting()
252 	struct drm_i915_private *dev_priv = to_i915(dev);  in __intel_set_cpu_fifo_underrun_reporting()  local
253 	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in __intel_set_cpu_fifo_underrun_reporting()
256 	lockdep_assert_held(&dev_priv->irq_lock);  in __intel_set_cpu_fifo_underrun_reporting()
261 	if (HAS_GMCH_DISPLAY(dev_priv))  in __intel_set_cpu_fifo_underrun_reporting()
263 	else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))  in __intel_set_cpu_fifo_underrun_reporting()
265 	else if (IS_GEN7(dev_priv))  in __intel_set_cpu_fifo_underrun_reporting()
267 	else if (INTEL_GEN(dev_priv) >= 8)  in __intel_set_cpu_fifo_underrun_reporting()
289 bool intel_set_cpu_fifo_underrun_reporting(struct drm_i915_private *dev_priv,  in intel_set_cpu_fifo_underrun_reporting()  argument
295 	spin_lock_irqsave(&dev_priv->irq_lock, flags);  in intel_set_cpu_fifo_underrun_reporting()
296 	ret = __intel_set_cpu_fifo_underrun_reporting(&dev_priv->drm, pipe,  in intel_set_cpu_fifo_underrun_reporting()
298 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);  in intel_set_cpu_fifo_underrun_reporting()
317 bool intel_set_pch_fifo_underrun_reporting(struct drm_i915_private *dev_priv,  in intel_set_pch_fifo_underrun_reporting()  argument
322 		intel_get_crtc_for_pipe(dev_priv, pch_transcoder);  in intel_set_pch_fifo_underrun_reporting()
335 	spin_lock_irqsave(&dev_priv->irq_lock, flags);  in intel_set_pch_fifo_underrun_reporting()
340 	if (HAS_PCH_IBX(dev_priv))  in intel_set_pch_fifo_underrun_reporting()
341 		ibx_set_fifo_underrun_reporting(&dev_priv->drm,  in intel_set_pch_fifo_underrun_reporting()
345 		cpt_set_fifo_underrun_reporting(&dev_priv->drm,  in intel_set_pch_fifo_underrun_reporting()
349 	spin_unlock_irqrestore(&dev_priv->irq_lock, flags);  in intel_set_pch_fifo_underrun_reporting()
362 void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,  in intel_cpu_fifo_underrun_irq_handler()  argument
365 	struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);  in intel_cpu_fifo_underrun_irq_handler()
372 	if (HAS_GMCH_DISPLAY(dev_priv) &&  in intel_cpu_fifo_underrun_irq_handler()
376 	if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) {  in intel_cpu_fifo_underrun_irq_handler()
377 		trace_intel_cpu_fifo_underrun(dev_priv, pipe);  in intel_cpu_fifo_underrun_irq_handler()
382 	intel_fbc_handle_fifo_underrun_irq(dev_priv);  in intel_cpu_fifo_underrun_irq_handler()
394 void intel_pch_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv,  in intel_pch_fifo_underrun_irq_handler()  argument
397 	if (intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder,  in intel_pch_fifo_underrun_irq_handler()
399 		trace_intel_pch_fifo_underrun(dev_priv, pch_transcoder);  in intel_pch_fifo_underrun_irq_handler()
414 void intel_check_cpu_fifo_underruns(struct drm_i915_private *dev_priv)  in intel_check_cpu_fifo_underruns()  argument
418 	spin_lock_irq(&dev_priv->irq_lock);  in intel_check_cpu_fifo_underruns()
420 	for_each_intel_crtc(&dev_priv->drm, crtc) {  in intel_check_cpu_fifo_underruns()
424 		if (HAS_GMCH_DISPLAY(dev_priv))  in intel_check_cpu_fifo_underruns()
426 		else if (IS_GEN7(dev_priv))  in intel_check_cpu_fifo_underruns()
430 	spin_unlock_irq(&dev_priv->irq_lock);  in intel_check_cpu_fifo_underruns()
441 void intel_check_pch_fifo_underruns(struct drm_i915_private *dev_priv)  in intel_check_pch_fifo_underruns()  argument
445 	spin_lock_irq(&dev_priv->irq_lock);  in intel_check_pch_fifo_underruns()
447 	for_each_intel_crtc(&dev_priv->drm, crtc) {  in intel_check_pch_fifo_underruns()
451 		if (HAS_PCH_CPT(dev_priv))  in intel_check_pch_fifo_underruns()
455 	spin_unlock_irq(&dev_priv->irq_lock);  in intel_check_pch_fifo_underruns()