62 static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)  in get_crtc_fence_y_offset()  argument
64 	return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;  in get_crtc_fence_y_offset()
119 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;  in i8xx_fbc_activate()
167 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;  in g4x_fbc_activate()
213 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;  in ilk_fbc_activate()
215 	int threshold = dev_priv->fbc.threshold;  in ilk_fbc_activate()
280 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;  in gen7_fbc_activate()
282 	int threshold = dev_priv->fbc.threshold;  in gen7_fbc_activate()
328 	if (dev_priv->fbc.false_color)  in gen7_fbc_activate()
360 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_hw_activate()  local
362 	fbc->active = true;  in intel_fbc_hw_activate()
376 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_hw_deactivate()  local
378 	fbc->active = false;  in intel_fbc_hw_deactivate()
399 	return dev_priv->fbc.active;  in intel_fbc_is_active()
405 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_deactivate()  local
407 	WARN_ON(!mutex_is_locked(&fbc->lock));  in intel_fbc_deactivate()
409 	if (fbc->active)  in intel_fbc_deactivate()
412 	fbc->no_fbc_reason = reason;  in intel_fbc_deactivate()
419 	struct intel_fbc *fbc = &dev_priv->fbc;  in multiple_pipes_ok()  local
427 		fbc->visible_pipes_mask |= (1 << pipe);  in multiple_pipes_ok()
429 		fbc->visible_pipes_mask &= ~(1 << pipe);  in multiple_pipes_ok()
431 	return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;  in multiple_pipes_ok()
486 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_alloc_cfb()  local
490 	WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));  in intel_fbc_alloc_cfb()
492 	size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);  in intel_fbc_alloc_cfb()
493 	fb_cpp = fbc->state_cache.fb.format->cpp[0];  in intel_fbc_alloc_cfb()
495 	ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,  in intel_fbc_alloc_cfb()
504 	fbc->threshold = ret;  in intel_fbc_alloc_cfb()
507 		I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);  in intel_fbc_alloc_cfb()
509 		I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);  in intel_fbc_alloc_cfb()
520 		fbc->compressed_llb = compressed_llb;  in intel_fbc_alloc_cfb()
523 					     fbc->compressed_fb.start,  in intel_fbc_alloc_cfb()
526 					     fbc->compressed_llb->start,  in intel_fbc_alloc_cfb()
529 			   dev_priv->dsm.start + fbc->compressed_fb.start);  in intel_fbc_alloc_cfb()
535 		      fbc->compressed_fb.size, fbc->threshold);  in intel_fbc_alloc_cfb()
541 	i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);  in intel_fbc_alloc_cfb()
550 	struct intel_fbc *fbc = &dev_priv->fbc;  in __intel_fbc_cleanup_cfb()  local
552 	if (drm_mm_node_allocated(&fbc->compressed_fb))  in __intel_fbc_cleanup_cfb()
553 		i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);  in __intel_fbc_cleanup_cfb()
555 	if (fbc->compressed_llb) {  in __intel_fbc_cleanup_cfb()
556 		i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);  in __intel_fbc_cleanup_cfb()
557 		kfree(fbc->compressed_llb);  in __intel_fbc_cleanup_cfb()
563 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_cleanup_cfb()  local
568 	mutex_lock(&fbc->lock);  in intel_fbc_cleanup_cfb()
570 	mutex_unlock(&fbc->lock);  in intel_fbc_cleanup_cfb()
626 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_hw_tracking_covers_screen()  local
640 	intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,  in intel_fbc_hw_tracking_covers_screen()
642 	effective_w += fbc->state_cache.plane.adjusted_x;  in intel_fbc_hw_tracking_covers_screen()
643 	effective_h += fbc->state_cache.plane.adjusted_y;  in intel_fbc_hw_tracking_covers_screen()
653 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_update_state_cache()  local
654 	struct intel_fbc_state_cache *cache = &fbc->state_cache;  in intel_fbc_update_state_cache()
692 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_can_activate()  local
693 	struct intel_fbc_state_cache *cache = &fbc->state_cache;  in intel_fbc_can_activate()
698 	if (fbc->underrun_detected) {  in intel_fbc_can_activate()
699 		fbc->no_fbc_reason = "underrun detected";  in intel_fbc_can_activate()
704 		fbc->no_fbc_reason = "primary plane not visible";  in intel_fbc_can_activate()
709 		fbc->no_fbc_reason = "incompatible mode";  in intel_fbc_can_activate()
714 		fbc->no_fbc_reason = "mode too large for compression";  in intel_fbc_can_activate()
732 		fbc->no_fbc_reason = "framebuffer not tiled or fenced";  in intel_fbc_can_activate()
737 		fbc->no_fbc_reason = "rotation unsupported";  in intel_fbc_can_activate()
742 		fbc->no_fbc_reason = "framebuffer stride not supported";  in intel_fbc_can_activate()
747 		fbc->no_fbc_reason = "pixel format is invalid";  in intel_fbc_can_activate()
754 		fbc->no_fbc_reason = "pixel rate is too big";  in intel_fbc_can_activate()
768 	if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >  in intel_fbc_can_activate()
769 	    fbc->compressed_fb.size * fbc->threshold) {  in intel_fbc_can_activate()
770 		fbc->no_fbc_reason = "CFB requirements changed";  in intel_fbc_can_activate()
780 	    (fbc->state_cache.plane.adjusted_y & 3)) {  in intel_fbc_can_activate()
781 		fbc->no_fbc_reason = "plane Y offset is misaligned";  in intel_fbc_can_activate()
790 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_can_enable()  local
793 		fbc->no_fbc_reason = "VGPU is active";  in intel_fbc_can_enable()
798 		fbc->no_fbc_reason = "disabled per module param or by default";  in intel_fbc_can_enable()
802 	if (fbc->underrun_detected) {  in intel_fbc_can_enable()
803 		fbc->no_fbc_reason = "underrun detected";  in intel_fbc_can_enable()
814 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_get_reg_params()  local
815 	struct intel_fbc_state_cache *cache = &fbc->state_cache;  in intel_fbc_get_reg_params()
827 	params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);  in intel_fbc_get_reg_params()
836 						32 * fbc->threshold) * 8;  in intel_fbc_get_reg_params()
844 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_pre_update()  local
850 	mutex_lock(&fbc->lock);  in intel_fbc_pre_update()
857 	if (!fbc->enabled || fbc->crtc != crtc)  in intel_fbc_pre_update()
861 	fbc->flip_pending = true;  in intel_fbc_pre_update()
866 	mutex_unlock(&fbc->lock);  in intel_fbc_pre_update()
878 	struct intel_fbc *fbc = &dev_priv->fbc;  in __intel_fbc_disable()  local
879 	struct intel_crtc *crtc = fbc->crtc;  in __intel_fbc_disable()
881 	WARN_ON(!mutex_is_locked(&fbc->lock));  in __intel_fbc_disable()
882 	WARN_ON(!fbc->enabled);  in __intel_fbc_disable()
883 	WARN_ON(fbc->active);  in __intel_fbc_disable()
889 	fbc->enabled = false;  in __intel_fbc_disable()
890 	fbc->crtc = NULL;  in __intel_fbc_disable()
896 	struct intel_fbc *fbc = &dev_priv->fbc;  in __intel_fbc_post_update()  local
898 	WARN_ON(!mutex_is_locked(&fbc->lock));  in __intel_fbc_post_update()
900 	if (!fbc->enabled || fbc->crtc != crtc)  in __intel_fbc_post_update()
903 	fbc->flip_pending = false;  in __intel_fbc_post_update()
904 	WARN_ON(fbc->active);  in __intel_fbc_post_update()
913 	intel_fbc_get_reg_params(crtc, &fbc->params);  in __intel_fbc_post_update()
918 	if (!fbc->busy_bits) {  in __intel_fbc_post_update()
928 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_post_update()  local
933 	mutex_lock(&fbc->lock);  in intel_fbc_post_update()
935 	mutex_unlock(&fbc->lock);  in intel_fbc_post_update()
938 static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)  in intel_fbc_get_frontbuffer_bit()  argument
940 	if (fbc->enabled)  in intel_fbc_get_frontbuffer_bit()
941 		return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;  in intel_fbc_get_frontbuffer_bit()
943 		return fbc->possible_framebuffer_bits;  in intel_fbc_get_frontbuffer_bit()
950 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_invalidate()  local
958 	mutex_lock(&fbc->lock);  in intel_fbc_invalidate()
960 	fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;  in intel_fbc_invalidate()
962 	if (fbc->enabled && fbc->busy_bits)  in intel_fbc_invalidate()
965 	mutex_unlock(&fbc->lock);  in intel_fbc_invalidate()
971 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_flush()  local
976 	mutex_lock(&fbc->lock);  in intel_fbc_flush()
978 	fbc->busy_bits &= ~frontbuffer_bits;  in intel_fbc_flush()
983 	if (!fbc->busy_bits && fbc->enabled &&  in intel_fbc_flush()
984 	    (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {  in intel_fbc_flush()
985 		if (fbc->active)  in intel_fbc_flush()
987 		else if (!fbc->flip_pending)  in intel_fbc_flush()
988 			__intel_fbc_post_update(fbc->crtc);  in intel_fbc_flush()
992 	mutex_unlock(&fbc->lock);  in intel_fbc_flush()
1010 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_choose_crtc()  local
1016 	mutex_lock(&fbc->lock);  in intel_fbc_choose_crtc()
1019 	if (fbc->crtc &&  in intel_fbc_choose_crtc()
1020 	    !intel_atomic_get_new_crtc_state(state, fbc->crtc))  in intel_fbc_choose_crtc()
1048 		fbc->no_fbc_reason = "no suitable CRTC for FBC";  in intel_fbc_choose_crtc()
1051 	mutex_unlock(&fbc->lock);  in intel_fbc_choose_crtc()
1070 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_enable()  local
1075 	mutex_lock(&fbc->lock);  in intel_fbc_enable()
1077 	if (fbc->enabled) {  in intel_fbc_enable()
1078 		WARN_ON(fbc->crtc == NULL);  in intel_fbc_enable()
1079 		if (fbc->crtc == crtc) {  in intel_fbc_enable()
1081 			WARN_ON(fbc->active);  in intel_fbc_enable()
1089 	WARN_ON(fbc->active);  in intel_fbc_enable()
1090 	WARN_ON(fbc->crtc != NULL);  in intel_fbc_enable()
1094 		fbc->no_fbc_reason = "not enough stolen memory";  in intel_fbc_enable()
1099 	fbc->no_fbc_reason = "FBC enabled but not active yet\n";  in intel_fbc_enable()
1101 	fbc->enabled = true;  in intel_fbc_enable()
1102 	fbc->crtc = crtc;  in intel_fbc_enable()
1104 	mutex_unlock(&fbc->lock);  in intel_fbc_enable()
1116 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_disable()  local
1123 	mutex_lock(&fbc->lock);  in intel_fbc_disable()
1124 	if (fbc->crtc == crtc)  in intel_fbc_disable()
1126 	mutex_unlock(&fbc->lock);  in intel_fbc_disable()
1137 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_global_disable()  local
1142 	mutex_lock(&fbc->lock);  in intel_fbc_global_disable()
1143 	if (fbc->enabled) {  in intel_fbc_global_disable()
1144 		WARN_ON(fbc->crtc->active);  in intel_fbc_global_disable()
1147 	mutex_unlock(&fbc->lock);  in intel_fbc_global_disable()
1153 		container_of(work, struct drm_i915_private, fbc.underrun_work);  in intel_fbc_underrun_work_fn()
1154 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_underrun_work_fn()  local
1156 	mutex_lock(&fbc->lock);  in intel_fbc_underrun_work_fn()
1159 	if (fbc->underrun_detected || !fbc->enabled)  in intel_fbc_underrun_work_fn()
1163 	fbc->underrun_detected = true;  in intel_fbc_underrun_work_fn()
1167 	mutex_unlock(&fbc->lock);  in intel_fbc_underrun_work_fn()
1181 	cancel_work_sync(&dev_priv->fbc.underrun_work);  in intel_fbc_reset_underrun()
1183 	ret = mutex_lock_interruptible(&dev_priv->fbc.lock);  in intel_fbc_reset_underrun()
1187 	if (dev_priv->fbc.underrun_detected) {  in intel_fbc_reset_underrun()
1189 		dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";  in intel_fbc_reset_underrun()
1192 	dev_priv->fbc.underrun_detected = false;  in intel_fbc_reset_underrun()
1193 	mutex_unlock(&dev_priv->fbc.lock);  in intel_fbc_reset_underrun()
1214 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_handle_fifo_underrun_irq()  local
1225 	if (READ_ONCE(fbc->underrun_detected))  in intel_fbc_handle_fifo_underrun_irq()
1228 	schedule_work(&fbc->underrun_work);  in intel_fbc_handle_fifo_underrun_irq()
1250 			dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);  in intel_fbc_init_pipe_state()
1296 	struct intel_fbc *fbc = &dev_priv->fbc;  in intel_fbc_init()  local
1298 	INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);  in intel_fbc_init()
1299 	mutex_init(&fbc->lock);  in intel_fbc_init()
1300 	fbc->enabled = false;  in intel_fbc_init()
1301 	fbc->active = false;  in intel_fbc_init()
1311 		fbc->no_fbc_reason = "unsupported by this chipset";  in intel_fbc_init()