1061 struct intel_dp {  struct
1062 	i915_reg_t output_reg;
1063 	uint32_t DP;
1064 	int link_rate;
1065 	uint8_t lane_count;
1066 	uint8_t sink_count;
1067 	bool link_mst;
1068 	bool link_trained;
1069 	bool has_audio;
1070 	bool detect_done;
1071 	bool reset_link_params;
1072 	enum aux_ch aux_ch;
1073 	uint8_t dpcd[DP_RECEIVER_CAP_SIZE];
1074 	uint8_t psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE];
1075 	uint8_t downstream_ports[DP_MAX_DOWNSTREAM_PORTS];
1076 	uint8_t edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
1078 	int num_source_rates;
1079 	const int *source_rates;
1081 	int num_sink_rates;
1082 	int sink_rates[DP_MAX_SUPPORTED_RATES];
1083 	bool use_rate_select;
1085 	int num_common_rates;
1086 	int common_rates[DP_MAX_SUPPORTED_RATES];
1088 	int max_link_lane_count;
1090 	int max_link_rate;
1092 	struct drm_dp_desc desc;
1093 	struct drm_dp_aux aux;
1094 	enum intel_display_power_domain aux_power_domain;
1095 	uint8_t train_set[4];
1096 	int panel_power_up_delay;
1097 	int panel_power_down_delay;
1098 	int panel_power_cycle_delay;
1099 	int backlight_on_delay;
1100 	int backlight_off_delay;
1101 	struct delayed_work panel_vdd_work;
1102 	bool want_panel_vdd;
1103 	unsigned long last_power_on;
1104 	unsigned long last_backlight_off;
1105 	ktime_t panel_power_off_time;
1107 	struct notifier_block edp_notifier;
1134 	struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];  argument
1137 	uint32_t (*get_aux_clock_divider)(struct intel_dp *dp, int index);  argument
1142 	uint32_t (*get_aux_send_ctl)(struct intel_dp *dp,  argument
1146 	i915_reg_t (*aux_ch_ctl_reg)(struct intel_dp *dp);  argument
1147 	i915_reg_t (*aux_ch_data_reg)(struct intel_dp *dp, int index);  argument
1150 	void (*prepare_link_retrain)(struct intel_dp *intel_dp);  argument
1153 	struct intel_dp_compliance compliance;  argument
1306 dp_to_dig_port(struct intel_dp *intel_dp)  in dp_to_dig_port()
1312 dp_to_lspcon(struct intel_dp *intel_dp)  in dp_to_lspcon()