Lines Matching defs:intel_crtc_state

712 struct intel_crtc_state {  struct
713 	struct drm_crtc_state base;
724 	unsigned long quirks;
726 	unsigned fb_bits; /* framebuffers to flip */
727 	bool update_pipe; /* can a fast modeset be performed? */
728 	bool disable_cxsr;
729 	bool update_wm_pre, update_wm_post; /* watermarks are updated */
730 	bool fb_changed; /* fb on any of the planes is changed */
731 	bool fifo_changed; /* FIFO split is changed */
736 	int pipe_src_w, pipe_src_h;
742 	unsigned int pixel_rate;
746 	bool has_pch_encoder;
749 	bool has_infoframe;
754 	enum transcoder cpu_transcoder;
760 	bool limited_color_range;
765 	unsigned int output_types;
768 	bool has_hdmi_sink;
772 	bool has_audio;
778 	bool dither;
786 	bool dither_force_disable;
789 	bool clock_set;
793 	bool sdvo_tv_clock;
800 	bool bw_constrained;
804 	struct dpll dpll;
807 	struct intel_shared_dpll *shared_dpll;
810 	struct intel_dpll_hw_state dpll_hw_state;
813 	struct {
815 	} dsi_pll;
817 	int pipe_bpp;
818 	struct intel_link_m_n dp_m_n;
821 	struct intel_link_m_n dp_m2_n2;
822 	bool has_drrs;
824 	bool has_psr;
825 	bool has_psr2;
832 	int port_clock;
835 	unsigned pixel_multiplier;
837 	uint8_t lane_count;
843 	uint8_t lane_lat_optim_mask;
846 	u8 min_voltage_level;
849 	struct {
853 	} gmch_pfit;
856 	struct {
861 	} pch_pfit;
864 	int fdi_lanes;
865 	struct intel_link_m_n fdi_m_n;
867 	bool ips_enabled;
868 	bool ips_force_disable;
870 	bool enable_fbc;
872 	bool double_wide;
874 	int pbn;
876 	struct intel_crtc_scaler_state scaler_state;
879 	enum pipe hsw_workaround_pipe;
882 	bool disable_lp_wm;
884 	struct intel_crtc_wm_state wm;
887 	uint32_t gamma_mode;
890 	u8 active_planes;
891 	u8 nv12_planes;
916 	struct intel_crtc_state *config;  argument