Lines Matching refs:ctrl1
938 val |= pll->state.hw_state.ctrl1 << (id * 6); in skl_ddi_pll_write_ctrl1()
1011 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_pll_get_hw_state()
1046 hw_state->ctrl1 = (val >> (id * 6)) & 0x3f; in skl_ddi_dpll0_get_hw_state()
1306 uint32_t ctrl1, cfgcr1, cfgcr2; in skl_ddi_hdmi_pll_dividers() local
1313 ctrl1 = DPLL_CTRL1_OVERRIDE(0); in skl_ddi_hdmi_pll_dividers()
1315 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); in skl_ddi_hdmi_pll_dividers()
1333 crtc_state->dpll_hw_state.ctrl1 = ctrl1; in skl_ddi_hdmi_pll_dividers()
1343 uint32_t ctrl1; in skl_ddi_dp_set_dpll_hw_state() local
1349 ctrl1 = DPLL_CTRL1_OVERRIDE(0); in skl_ddi_dp_set_dpll_hw_state()
1352 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); in skl_ddi_dp_set_dpll_hw_state()
1355 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); in skl_ddi_dp_set_dpll_hw_state()
1358 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); in skl_ddi_dp_set_dpll_hw_state()
1362 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0); in skl_ddi_dp_set_dpll_hw_state()
1365 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0); in skl_ddi_dp_set_dpll_hw_state()
1368 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0); in skl_ddi_dp_set_dpll_hw_state()
1372 dpll_hw_state->ctrl1 = ctrl1; in skl_ddi_dp_set_dpll_hw_state()
1425 hw_state->ctrl1, in skl_dump_hw_state()